📄 mult.rpt
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E22 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 0/2 0/2 10/22( 45%)
E23 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 12/22( 54%)
E24 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
E25 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
E26 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
E27 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 7/22( 31%)
E28 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 8/22( 36%)
E29 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
E30 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 12/22( 54%)
E31 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 8/22( 36%)
E32 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 12/22( 54%)
E33 3/ 8( 37%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 4/22( 18%)
E34 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
E35 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 8/22( 36%)
E36 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 10/22( 45%)
F1 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
F2 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
F3 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 14/22( 63%)
F4 3/ 8( 37%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 6/22( 27%)
F5 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
F6 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 7/22( 31%)
F7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
F9 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
F10 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 8/22( 36%)
F11 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 8/22( 36%)
F12 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
F13 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
F14 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 7/22( 31%)
F15 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 15/22( 68%)
F16 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
F18 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 8/22( 36%)
F19 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
F20 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 8/22( 36%)
F21 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 11/22( 50%)
F22 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
F24 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
F25 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 8/22( 36%)
F26 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
F27 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
F29 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
F30 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 12/22( 54%)
F31 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
F32 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 12/22( 54%)
F33 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 11/22( 50%)
F34 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 12/22( 54%)
F35 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
F36 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 58/96 ( 60%)
Total logic cells used: 733/1728 ( 42%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.56/4 ( 89%)
Total fan-in: 2615/6912 ( 37%)
Total input pins required: 32
Total input I/O cell registers required: 0
Total output pins required: 32
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 733
Total flipflops required: 0
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 235/1728 ( 13%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 7 0 0 0 8 0 8 0 8 0 0 0 0 2 8 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 43/0
B: 1 8 0 0 1 2 0 8 2 8 0 0 8 8 8 8 0 0 0 6 8 7 8 8 8 8 8 0 2 0 8 1 7 8 2 8 0 159/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 8 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 2 7 7 8 8 8 8 8 8 8 7 8 0 8 8 8 0 8 135/0
E: 0 0 0 2 0 0 0 0 0 0 0 7 0 0 8 0 8 0 0 8 8 7 8 8 8 8 8 8 7 8 8 8 8 3 8 7 8 161/0
F: 1 8 8 3 7 7 1 0 8 8 8 8 8 8 8 8 0 8 0 8 8 8 8 0 8 8 8 8 0 8 8 8 8 8 8 8 8 235/0
Total: 10 23 8 5 8 17 1 16 10 32 8 15 16 16 26 24 8 9 0 24 31 29 32 24 32 32 32 25 17 23 32 17 31 27 26 23 24 733/0
Device-Specific Information: d:\2fsk\mult.rpt
mult
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
48 - - - 24 INPUT ^ 0 0 0 33 a0
144 - - - 36 INPUT ^ 0 0 0 35 a1
46 - - - 27 INPUT ^ 0 0 0 40 a2
56 - - - -- INPUT ^ 0 0 0 41 a3
125 - - - -- INPUT ^ 0 0 0 39 a4
142 - - - 34 INPUT ^ 0 0 0 40 a5
54 - - - -- INPUT ^ 0 0 0 42 a6
51 - - - 20 INPUT ^ 0 0 0 42 a7
140 - - - 32 INPUT ^ 0 0 0 42 a8
124 - - - -- INPUT ^ 0 0 0 42 a9
86 - - E -- INPUT ^ 0 0 0 42 a10
116 - - - 07 INPUT ^ 0 0 0 40 a11
126 - - - -- INPUT ^ 0 0 0 43 a12
59 - - - 16 INPUT ^ 0 0 0 40 a13
117 - - - 08 INPUT ^ 0 0 0 42 a14
72 - - - 03 INPUT ^ 0 0 0 36 a15
73 - - - 01 INPUT ^ 0 0 0 45 b0
109 - - - 01 INPUT ^ 0 0 0 47 b1
70 - - - 05 INPUT ^ 0 0 0 34 b2
62 - - - 12 INPUT ^ 0 0 0 46 b3
65 - - - 09 INPUT ^ 0 0 0 46 b4
120 - - - 14 INPUT ^ 0 0 0 33 b5
133 - - - 28 INPUT ^ 0 0 0 46 b6
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