📄 parity.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\2fsk\parity.rpt
parity
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 21 OR2 s 3 0 0 1 |lpm_xor:14|xor_cascade0_7~1
- 2 - A 21 OR2 s 2 1 0 2 |lpm_xor:14|xor_cascade0_7~2
- 8 - A 21 OR2 s 3 1 1 0 |lpm_xor:14|xor_cascade0_7~3
- 3 - A 21 OR2 3 1 1 0 |lpm_xor:14|xor_cascade0_7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\2fsk\parity.rpt
parity
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/ 96( 3%) 0/ 48( 0%) 1/ 48( 2%) 2/16( 12%) 2/16( 12%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\2fsk\parity.rpt
parity
** EQUATIONS **
input_bus0 : INPUT;
input_bus1 : INPUT;
input_bus2 : INPUT;
input_bus3 : INPUT;
input_bus4 : INPUT;
input_bus5 : INPUT;
input_bus6 : INPUT;
input_bus7 : INPUT;
-- Node name is 'even_bit'
-- Equation name is 'even_bit', type is output
even_bit = !_LC8_A21;
-- Node name is 'odd_bit'
-- Equation name is 'odd_bit', type is output
odd_bit = _LC3_A21;
-- Node name is '|lpm_xor:14|xor_cascade0_7~1' from file "lpm_xor.tdf" line 63, column 22
-- Equation name is '_LC1_A21', type is buried
-- synthesized logic cell
_LC1_A21 = LCELL( _EQ001);
_EQ001 = input_bus0 & input_bus1 & input_bus2
# !input_bus0 & !input_bus1 & input_bus2
# !input_bus0 & input_bus1 & !input_bus2
# input_bus0 & !input_bus1 & !input_bus2;
-- Node name is '|lpm_xor:14|xor_cascade0_7~2' from file "lpm_xor.tdf" line 63, column 22
-- Equation name is '_LC2_A21', type is buried
-- synthesized logic cell
_LC2_A21 = LCELL( _EQ002);
_EQ002 = input_bus3 & input_bus4 & _LC1_A21
# !input_bus3 & input_bus4 & !_LC1_A21
# input_bus3 & !input_bus4 & !_LC1_A21
# !input_bus3 & !input_bus4 & _LC1_A21;
-- Node name is '|lpm_xor:14|xor_cascade0_7~3' from file "lpm_xor.tdf" line 63, column 22
-- Equation name is '_LC8_A21', type is buried
-- synthesized logic cell
_LC8_A21 = LCELL( _EQ003);
_EQ003 = input_bus5 & !input_bus6 & !input_bus7 & !_LC2_A21
# !input_bus5 & !input_bus6 & !input_bus7 & _LC2_A21
# input_bus5 & input_bus6 & !input_bus7 & _LC2_A21
# !input_bus5 & input_bus6 & !input_bus7 & !_LC2_A21
# input_bus5 & input_bus6 & input_bus7 & !_LC2_A21
# !input_bus5 & input_bus6 & input_bus7 & _LC2_A21
# input_bus5 & !input_bus6 & input_bus7 & _LC2_A21
# !input_bus5 & !input_bus6 & input_bus7 & !_LC2_A21;
-- Node name is '|lpm_xor:14|xor_cascade0_7' from file "lpm_xor.tdf" line 63, column 22
-- Equation name is '_LC3_A21', type is buried
_LC3_A21 = LCELL( _EQ004);
_EQ004 = input_bus5 & input_bus6 & input_bus7 & !_LC2_A21
# !input_bus5 & input_bus6 & input_bus7 & _LC2_A21
# input_bus5 & !input_bus6 & input_bus7 & _LC2_A21
# !input_bus5 & !input_bus6 & input_bus7 & !_LC2_A21
# input_bus5 & input_bus6 & !input_bus7 & _LC2_A21
# !input_bus5 & input_bus6 & !input_bus7 & !_LC2_A21
# input_bus5 & !input_bus6 & !input_bus7 & !_LC2_A21
# !input_bus5 & !input_bus6 & !input_bus7 & _LC2_A21;
Project Information d:\2fsk\parity.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,700K
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