📄 down_count.rpt
字号:
14 - - B -- OUTPUT 0 1 0 0 out8
61 - - B -- OUTPUT 0 1 0 0 out9
57 - - C -- OUTPUT 0 1 0 0 out10
55 - - C -- OUTPUT 0 1 0 0 out11
58 - - C -- OUTPUT 0 1 0 0 out12
48 - - - 07 OUTPUT 0 1 0 0 out13
64 - - B -- OUTPUT 0 1 0 0 out14
62 - - B -- OUTPUT 0 1 0 0 out15
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\2fsk\down_count.rpt
down_count
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - A 05 OR2 0 2 0 1 |lpm_add_sub:132|addcore:adder|pcarry1
- 6 - A 05 OR2 0 3 0 1 |lpm_add_sub:132|addcore:adder|pcarry2
- 8 - A 05 OR2 0 4 0 4 |lpm_add_sub:132|addcore:adder|pcarry3
- 4 - C 05 OR2 0 2 0 1 |lpm_add_sub:132|addcore:adder|pcarry4
- 1 - B 02 OR2 0 3 0 1 |lpm_add_sub:132|addcore:adder|pcarry5
- 6 - B 02 OR2 0 4 0 4 |lpm_add_sub:132|addcore:adder|pcarry6
- 8 - B 02 OR2 0 2 0 1 |lpm_add_sub:132|addcore:adder|pcarry7
- 5 - B 02 OR2 0 3 0 1 |lpm_add_sub:132|addcore:adder|pcarry8
- 4 - B 02 OR2 0 4 0 4 |lpm_add_sub:132|addcore:adder|pcarry9
- 5 - C 05 OR2 0 2 0 1 |lpm_add_sub:132|addcore:adder|pcarry10
- 6 - C 05 OR2 0 3 0 1 |lpm_add_sub:132|addcore:adder|pcarry11
- 2 - C 05 OR2 0 4 0 4 |lpm_add_sub:132|addcore:adder|pcarry12
- 4 - B 07 OR2 0 2 0 1 |lpm_add_sub:132|addcore:adder|pcarry13
- 5 - B 07 OR2 0 3 0 1 |lpm_add_sub:132|addcore:adder|pcarry14
- 6 - B 07 DFFE + 2 1 1 1 :88
- 2 - B 07 DFFE + 2 1 1 2 :89
- 3 - B 07 DFFE + 2 1 1 3 :90
- 1 - C 05 DFFE + 2 1 1 1 :91
- 7 - C 05 DFFE + 2 1 1 2 :92
- 3 - C 05 DFFE + 2 1 1 3 :93
- 8 - B 07 DFFE + 2 1 1 1 :94
- 2 - B 02 DFFE + 2 1 1 2 :95
- 3 - B 02 DFFE + 2 1 1 3 :96
- 7 - B 02 DFFE + 2 1 1 1 :97
- 8 - C 05 DFFE + 2 1 1 2 :98
- 2 - A 05 DFFE + 2 1 1 3 :99
- 1 - A 05 DFFE + 2 1 1 1 :100
- 3 - A 05 DFFE + 2 1 1 2 :101
- 5 - A 05 DFFE + 2 1 1 3 :102
- 7 - A 05 DFFE + 2 0 1 4 :103
- 1 - B 07 AND2 0 4 1 0 :104
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\2fsk\down_count.rpt
down_count
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 4/ 48( 8%) 0/ 48( 0%) 2/16( 12%) 4/16( 25%) 0/16( 0%)
B: 11/ 96( 11%) 6/ 48( 12%) 0/ 48( 0%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
C: 7/ 96( 7%) 3/ 48( 6%) 0/ 48( 0%) 4/16( 25%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\2fsk\down_count.rpt
down_count
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 clk
Device-Specific Information: d:\2fsk\down_count.rpt
down_count
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 16 clear
Device-Specific Information: d:\2fsk\down_count.rpt
down_count
** EQUATIONS **
clear : INPUT;
clk : INPUT;
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
d4 : INPUT;
d5 : INPUT;
d6 : INPUT;
d7 : INPUT;
d8 : INPUT;
d9 : INPUT;
d10 : INPUT;
d11 : INPUT;
d12 : INPUT;
d13 : INPUT;
d14 : INPUT;
d15 : INPUT;
load : INPUT;
-- Node name is 'B0'
-- Equation name is 'B0', type is output
B0 = _LC1_B7;
-- Node name is 'out0'
-- Equation name is 'out0', type is output
out0 = _LC7_A5;
-- Node name is 'out1'
-- Equation name is 'out1', type is output
out1 = _LC5_A5;
-- Node name is 'out2'
-- Equation name is 'out2', type is output
out2 = _LC3_A5;
-- Node name is 'out3'
-- Equation name is 'out3', type is output
out3 = _LC1_A5;
-- Node name is 'out4'
-- Equation name is 'out4', type is output
out4 = _LC2_A5;
-- Node name is 'out5'
-- Equation name is 'out5', type is output
out5 = _LC8_C5;
-- Node name is 'out6'
-- Equation name is 'out6', type is output
out6 = _LC7_B2;
-- Node name is 'out7'
-- Equation name is 'out7', type is output
out7 = _LC3_B2;
-- Node name is 'out8'
-- Equation name is 'out8', type is output
out8 = _LC2_B2;
-- Node name is 'out9'
-- Equation name is 'out9', type is output
out9 = _LC8_B7;
-- Node name is 'out10'
-- Equation name is 'out10', type is output
out10 = _LC3_C5;
-- Node name is 'out11'
-- Equation name is 'out11', type is output
out11 = _LC7_C5;
-- Node name is 'out12'
-- Equation name is 'out12', type is output
out12 = _LC1_C5;
-- Node name is 'out13'
-- Equation name is 'out13', type is output
out13 = _LC3_B7;
-- Node name is 'out14'
-- Equation name is 'out14', type is output
out14 = _LC2_B7;
-- Node name is 'out15'
-- Equation name is 'out15', type is output
out15 = _LC6_B7;
-- Node name is '|lpm_add_sub:132|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_A5', type is buried
_LC4_A5 = LCELL( _EQ001);
_EQ001 = _LC5_A5
# _LC7_A5;
-- Node name is '|lpm_add_sub:132|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_A5', type is buried
_LC6_A5 = LCELL( _EQ002);
_EQ002 = _LC5_A5
# _LC7_A5
# _LC3_A5;
-- Node name is '|lpm_add_sub:132|addcore:adder|pcarry3' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC8_A5', type is buried
_LC8_A5 = LCELL( _EQ003);
_EQ003 = _LC5_A5
# _LC7_A5
# _LC3_A5
# _LC1_A5;
-- Node name is '|lpm_add_sub:132|addcore:adder|pcarry4' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_C5', type is buried
_LC4_C5 = LCELL( _EQ004);
_EQ004 = _LC2_A5
# _LC8_A5;
-- Node name is '|lpm_add_sub:132|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_B2', type is buried
_LC1_B2 = LCELL( _EQ005);
_EQ005 = _LC2_A5
# _LC8_A5
# _LC8_C5;
-- Node name is '|lpm_add_sub:132|addcore:adder|pcarry6' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_B2', type is buried
_LC6_B2 = LCELL( _EQ006);
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