📄 m.rpt
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Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------- LC21 All_Zero
| +----------------------- LC20 Delay_m0
| | +--------------------- LC24 Delay_m1
| | | +------------------- LC27 Delay_m2
| | | | +----------------- LC29 Delay_m3
| | | | | +--------------- LC17 Delay_m4
| | | | | | +------------- LC19 Delay_m5
| | | | | | | +----------- LC22 Delay_m6
| | | | | | | | +--------- LC23 Error_ind
| | | | | | | | | +------- LC30 Frame_Ind
| | | | | | | | | | +----- LC18 Main_CLK
| | | | | | | | | | | +--- LC28 m_test
| | | | | | | | | | | | +- LC26 MUX_DT
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC21 -> - - - - - - - * - - - - - | - * | <-- All_Zero
LC20 -> * - - - - - - * - - - - - | - * | <-- Delay_m0
LC24 -> * * - - - - - * - - - - - | - * | <-- Delay_m1
LC27 -> * - * - - - - * - - - - - | - * | <-- Delay_m2
LC29 -> * - - * - - - * - - - - - | - * | <-- Delay_m3
LC17 -> * - - - * - - * - - - - - | - * | <-- Delay_m4
LC19 -> * - - - - * - * - - - - - | - * | <-- Delay_m5
LC22 -> * - - - - - * - - - - * - | - * | <-- Delay_m6
LC18 -> - * * * * * * * - - - - - | - * | <-- Main_CLK
Pin
37 -> - - - - - - - - - - - - * | - * | <-- BCLKT
21 -> - - - - - - - - - - - - * | - * | <-- DT_PCM
41 -> - - - - - - - - - - - - * | - * | <-- Error_SEL0
40 -> - - - - - - - - - - - - * | - * | <-- Error_SEL1
4 -> - - - - - - - - - - - - * | - * | <-- FSX_PCM
5 -> - - - - - - - * - - - - - | - * | <-- m_SEL0
6 -> - - - - - - - * - - - - - | - * | <-- m_SEL1
8 -> - - - - - - - - - - - - * | - * | <-- m_Sequence
9 -> - - - - - - - - - - * - * | - * | <-- MUX_CLK
11 -> - - - - - - - - - - - - * | - * | <-- SW0
12 -> - - - - - - - - - - - - * | - * | <-- SW1
14 -> - - - - - - - - - - - - * | - * | <-- SW2
16 -> - - - - - - - - - - - - * | - * | <-- SW3
17 -> - - - - - - - - - - - - * | - * | <-- SW4
18 -> - - - - - - - - - - - - * | - * | <-- SW5
19 -> - - - - - - - - - - - - * | - * | <-- SW6
20 -> - - - - - - - - - - - - * | - * | <-- SW7
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\2fsk\m.rpt
m
** EQUATIONS **
BCLKT : INPUT;
DT_PCM : INPUT;
Error_SEL0 : INPUT;
Error_SEL1 : INPUT;
FSX_PCM : INPUT;
m_SEL0 : INPUT;
m_SEL1 : INPUT;
m_Sequence : INPUT;
MUX_CLK : INPUT;
SW0 : INPUT;
SW1 : INPUT;
SW2 : INPUT;
SW3 : INPUT;
SW4 : INPUT;
SW5 : INPUT;
SW6 : INPUT;
SW7 : INPUT;
-- Node name is 'All_Zero' from file "m.tdf" line 34, column 2
-- Equation name is 'All_Zero', location is LC021, type is buried.
All_Zero = LCELL( _EQ001 $ GND);
_EQ001 = !Delay_m0 & !Delay_m1 & !Delay_m2 & !Delay_m3 & !Delay_m4 &
!Delay_m5 & !Delay_m6;
-- Node name is 'Delay_m0' from file "m.tdf" line 30, column 9
-- Equation name is 'Delay_m0', location is LC020, type is buried.
Delay_m0 = DFFE( Delay_m1 $ GND, Main_CLK, VCC, VCC, VCC);
-- Node name is 'Delay_m1' from file "m.tdf" line 30, column 9
-- Equation name is 'Delay_m1', location is LC024, type is buried.
Delay_m1 = DFFE( Delay_m2 $ GND, Main_CLK, VCC, VCC, VCC);
-- Node name is 'Delay_m2' from file "m.tdf" line 30, column 9
-- Equation name is 'Delay_m2', location is LC027, type is buried.
Delay_m2 = DFFE( Delay_m3 $ GND, Main_CLK, VCC, VCC, VCC);
-- Node name is 'Delay_m3' from file "m.tdf" line 30, column 9
-- Equation name is 'Delay_m3', location is LC029, type is buried.
Delay_m3 = DFFE( Delay_m4 $ GND, Main_CLK, VCC, VCC, VCC);
-- Node name is 'Delay_m4' from file "m.tdf" line 30, column 9
-- Equation name is 'Delay_m4', location is LC017, type is buried.
Delay_m4 = DFFE( Delay_m5 $ GND, Main_CLK, VCC, VCC, VCC);
-- Node name is 'Delay_m5' from file "m.tdf" line 30, column 9
-- Equation name is 'Delay_m5', location is LC019, type is buried.
Delay_m5 = DFFE( Delay_m6 $ GND, Main_CLK, VCC, VCC, VCC);
-- Node name is 'Delay_m6' from file "m.tdf" line 30, column 9
-- Equation name is 'Delay_m6', location is LC022, type is buried.
Delay_m6 = DFFE( _EQ002 $ !All_Zero, Main_CLK, VCC, VCC, VCC);
_EQ002 = _X001 & _X002 & _X003 & _X004 & _X005 & _X006 & _X007 &
_X008 & _X009 & _X010 & _X011 & _X012;
_X001 = EXP( All_Zero & Delay_m0 & !Delay_m1 & Delay_m2 & Delay_m3 &
!Delay_m4 & Delay_m5);
_X002 = EXP(!Delay_m4 & Delay_m5 & !m_SEL0 & !m_SEL1);
_X003 = EXP( Delay_m0 & !Delay_m1 & m_SEL0 & m_SEL1);
_X004 = EXP( All_Zero & Delay_m0 & !Delay_m1 & Delay_m2 & !Delay_m3 &
Delay_m4 & !Delay_m5);
_X005 = EXP( Delay_m4 & !Delay_m5 & !m_SEL0 & !m_SEL1);
_X006 = EXP( Delay_m3 & !Delay_m4 & m_SEL0 & !m_SEL1);
_X007 = EXP(!Delay_m1 & Delay_m2 & !m_SEL0 & m_SEL1);
_X008 = EXP( Delay_m1 & !Delay_m2 & !m_SEL0 & m_SEL1);
_X009 = EXP(!Delay_m3 & Delay_m4 & m_SEL0 & !m_SEL1);
_X010 = EXP( All_Zero & !Delay_m0 & Delay_m1 & !Delay_m2 & Delay_m3 &
!Delay_m4 & Delay_m5);
_X011 = EXP(!Delay_m0 & Delay_m1 & m_SEL0 & m_SEL1);
_X012 = EXP( All_Zero & !Delay_m0 & Delay_m1 & !Delay_m2 & !Delay_m3 &
Delay_m4 & !Delay_m5);
-- Node name is 'Error_ind'
-- Equation name is 'Error_ind', location is LC023, type is output.
Error_ind = LCELL( GND $ GND);
-- Node name is 'Frame_Ind'
-- Equation name is 'Frame_Ind', location is LC030, type is output.
Frame_Ind = LCELL( GND $ GND);
-- Node name is 'Main_CLK' from file "m.tdf" line 29, column 2
-- Equation name is 'Main_CLK', location is LC018, type is buried.
Main_CLK = LCELL( MUX_CLK $ GND);
-- Node name is 'm_test' = 'm_Out' from file "m.tdf" line 31, column 2
-- Equation name is 'm_test', location is LC028, type is output.
m_test = LCELL( Delay_m6 $ GND);
-- Node name is 'MUX_DT'
-- Equation name is 'MUX_DT', location is LC026, type is output.
MUX_DT = LCELL( _EQ003 $ GND);
_EQ003 = !BCLKT & !DT_PCM & !Error_SEL0 & !Error_SEL1 & !FSX_PCM &
!m_Sequence & !MUX_CLK & !SW0 & !SW1 & !SW2 & !SW3 & !SW4 & !SW5 &
!SW6 & !SW7;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\2fsk\m.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 6,488K
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