📄 fp.rpt
字号:
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\2fsk\fp.rpt
fp
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 clk
Device-Specific Information: d:\2fsk\fp.rpt
fp
** EQUATIONS **
clk : INPUT;
innumber0 : INPUT;
innumber1 : INPUT;
innumber2 : INPUT;
innumber3 : INPUT;
innumber4 : INPUT;
innumber5 : INPUT;
innumber6 : INPUT;
innumber7 : INPUT;
-- Node name is ':89' = 'count0'
-- Equation name is 'count0', location is LC3_B13, type is buried.
count0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !count0
# !_LC8_B22;
-- Node name is ':88' = 'count1'
-- Equation name is 'count1', location is LC8_B13, type is buried.
count1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !count0 & count1 & _LC8_B22
# count0 & !count1 & _LC8_B22;
-- Node name is ':87' = 'count2'
-- Equation name is 'count2', location is LC1_B13, type is buried.
count2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !count1 & count2 & _LC8_B22
# !count0 & count2 & _LC8_B22
# count0 & count1 & !count2 & _LC8_B22;
-- Node name is ':86' = 'count3'
-- Equation name is 'count3', location is LC1_B24, type is buried.
count3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = count3 & !_LC2_B13 & _LC8_B22
# !count3 & _LC2_B13
# _LC2_B13 & !_LC8_B22;
-- Node name is ':85' = 'count4'
-- Equation name is 'count4', location is LC3_B24, type is buried.
count4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = count3 & !count4 & _LC2_B13 & _LC8_B22
# !count3 & count4 & _LC8_B22
# count4 & !_LC2_B13 & _LC8_B22;
-- Node name is ':84' = 'count5'
-- Equation name is 'count5', location is LC2_B14, type is buried.
count5 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = count5 & !_LC2_B24 & _LC8_B22
# !count5 & _LC2_B24
# _LC2_B24 & !_LC8_B22;
-- Node name is ':83' = 'count6'
-- Equation name is 'count6', location is LC4_B14, type is buried.
count6 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = count5 & !count6 & _LC2_B24 & _LC8_B22
# count6 & !_LC2_B24 & _LC8_B22
# !count5 & count6 & _LC8_B22;
-- Node name is ':82' = 'count7'
-- Equation name is 'count7', location is LC1_B14, type is buried.
count7 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !count7 & _LC3_B14
# _LC1_B22 & _LC3_B14
# count7 & !_LC1_B22 & !_LC3_B14;
-- Node name is 'out0'
-- Equation name is 'out0', type is output
out0 = _LC2_B22;
-- Node name is '|lpm_add_sub:100|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B13', type is buried
_LC2_B13 = LCELL( _EQ009);
_EQ009 = count0 & count1 & count2 & _LC8_B22;
-- Node name is '|lpm_add_sub:100|addcore:adder|:133' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B24', type is buried
_LC2_B24 = LCELL( _EQ010);
_EQ010 = count3 & count4 & _LC2_B13 & _LC8_B22;
-- Node name is '|lpm_add_sub:100|addcore:adder|:141' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B14', type is buried
_LC3_B14 = LCELL( _EQ011);
_EQ011 = count5 & count6 & _LC2_B24 & _LC8_B22;
-- Node name is '~11~1'
-- Equation name is '~11~1', location is LC5_B22, type is buried.
-- synthesized logic cell
_LC5_B22 = LCELL( _EQ012);
_EQ012 = count1 & count2 & innumber2 & innumber3
# count1 & !count2 & innumber2 & !innumber3
# !count1 & count2 & !innumber2 & innumber3
# !count1 & !count2 & !innumber2 & !innumber3;
-- Node name is '~11~2'
-- Equation name is '~11~2', location is LC6_B22, type is buried.
-- synthesized logic cell
_LC6_B22 = LCELL( _EQ013);
_EQ013 = count0 & count6 & innumber1 & innumber7
# !count0 & count6 & !innumber1 & innumber7
# count0 & !count6 & innumber1 & !innumber7
# !count0 & !count6 & !innumber1 & !innumber7;
-- Node name is '~11~3'
-- Equation name is '~11~3', location is LC7_B14, type is buried.
-- synthesized logic cell
_LC7_B14 = LCELL( _EQ014);
_EQ014 = count5 & !count7 & innumber6
# !count5 & !count7 & !innumber6;
-- Node name is '~11~4'
-- Equation name is '~11~4', location is LC8_B24, type is buried.
-- synthesized logic cell
_LC8_B24 = LCELL( _EQ015);
_EQ015 = count3 & count4 & innumber4 & innumber5
# count3 & !count4 & innumber4 & !innumber5
# !count3 & count4 & !innumber4 & innumber5
# !count3 & !count4 & !innumber4 & !innumber5;
-- Node name is ':11'
-- Equation name is '_LC7_B22', type is buried
_LC7_B22 = LCELL( _EQ016);
_EQ016 = _LC5_B22 & _LC6_B22 & _LC7_B14 & _LC8_B24;
-- Node name is '~21~1'
-- Equation name is '~21~1', location is LC3_B22, type is buried.
-- synthesized logic cell
_LC3_B22 = LCELL( _EQ017);
_EQ017 = count7 & !innumber7
# !count7 & innumber7
# count0 & !innumber0
# !count0 & innumber0;
-- Node name is '~21~2'
-- Equation name is '~21~2', location is LC4_B22, type is buried.
-- synthesized logic cell
_LC4_B22 = LCELL( _EQ018);
_EQ018 = count2 & !innumber2
# !count2 & innumber2
# !count1 & innumber1
# count1 & !innumber1;
-- Node name is '~21~3'
-- Equation name is '~21~3', location is LC7_B24, type is buried.
-- synthesized logic cell
_LC7_B24 = LCELL( _EQ019);
_EQ019 = count4 & !innumber4
# !count4 & innumber4
# count3 & !innumber3
# !count3 & innumber3;
-- Node name is '~21~4'
-- Equation name is '~21~4', location is LC6_B14, type is buried.
-- synthesized logic cell
_LC6_B14 = LCELL( _EQ020);
_EQ020 = !count6 & innumber6
# count6 & !innumber6
# !count5 & innumber5
# count5 & !innumber5;
-- Node name is ':21'
-- Equation name is '_LC1_B22', type is buried
!_LC1_B22 = _LC1_B22~NOT;
_LC1_B22~NOT = LCELL( _EQ021);
_EQ021 = _LC3_B22
# _LC4_B22
# _LC7_B24
# _LC6_B14;
-- Node name is '~67~1'
-- Equation name is '~67~1', location is LC8_B22, type is buried.
-- synthesized logic cell
_LC8_B22 = LCELL( _EQ022);
_EQ022 = !_LC1_B22
# _LC7_B22;
-- Node name is ':99'
-- Equation name is '_LC2_B22', type is buried
_LC2_B22 = DFFE( _EQ023, GLOBAL( clk), VCC, VCC, VCC);
_EQ023 = !_LC2_B22 & _LC7_B22
# !_LC1_B22 & _LC2_B22 & !_LC7_B22
# _LC1_B22 & !_LC2_B22;
Project Information d:\2fsk\fp.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,220K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -