📄 fpq.rpt
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# _LC7_A8;
-- Node name is '~176~3'
-- Equation name is '~176~3', location is LC3_A10, type is buried.
-- synthesized logic cell
_LC3_A10 = LCELL( _EQ072);
_EQ072 = _LC6_A10 & !size5
# !_LC6_A10 & size5
# _LC7_A10 & !size2
# !_LC7_A10 & size2;
-- Node name is '~176~4'
-- Equation name is '~176~4', location is LC2_A2, type is buried.
-- synthesized logic cell
_LC2_A2 = LCELL( _EQ073);
_EQ073 = _LC1_A2
# _LC8_A8
# !_LC3_A1
# _LC3_A10;
-- Node name is '~176~5'
-- Equation name is '~176~5', location is LC5_A2, type is buried.
-- synthesized logic cell
_LC5_A2 = LCELL( _EQ074);
_EQ074 = _LC3_A2 & !size3
# !_LC3_A2 & size3
# _LC4_A2 & !size6
# !_LC4_A2 & size6;
-- Node name is ':177'
-- Equation name is '_LC6_A8', type is buried
!_LC6_A8 = _LC6_A8~NOT;
_LC6_A8~NOT = LCELL( _EQ075);
_EQ075 = !_LC1_A1 & !size1 & !s0
# size1 & s0
# _LC1_A1 & size1;
-- Node name is ':184'
-- Equation name is '_LC3_A1', type is buried
!_LC3_A1 = _LC3_A1~NOT;
_LC3_A1~NOT = LCELL( _EQ076);
_EQ076 = !_LC1_A1 & !_LC1_A6 & !size8 & s7
# !_LC1_A1 & _LC1_A6 & !size8 & !s7
# _LC1_A6 & size8 & s7
# !_LC1_A6 & size8 & !s7
# _LC1_A1 & size8;
-- Node name is '~194~1'
-- Equation name is '~194~1', location is LC6_A2, type is buried.
-- synthesized logic cell
_LC6_A2 = LCELL( _EQ077);
_EQ077 = _LC2_A2 & _LC8_A2
# _LC5_A2 & _LC8_A2
# _LC1_A1 & _LC2_A2
# _LC1_A1 & _LC5_A2;
-- Node name is ':198'
-- Equation name is '_LC8_A2', type is buried
_LC8_A2 = DFFE( _EQ078, GLOBAL( clk), VCC, VCC, VCC);
_EQ078 = _LC6_A2 & reset & size0
# _LC7_A2 & reset & !size0;
-- Node name is '~264~1'
-- Equation name is '~264~1', location is LC1_C8, type is buried.
-- synthesized logic cell
_LC1_C8 = LCELL( _EQ079);
_EQ079 = !reset
# !size0;
-- Node name is '~284~1'
-- Equation name is '~284~1', location is LC5_C9, type is buried.
-- synthesized logic cell
_LC5_C9 = LCELL( _EQ080);
_EQ080 = size1 & s10 & s11
# size1 & !s10 & !s11
# !size1 & s10 & !s11
# !size1 & !s10 & s11
# size0 & s10
# !size0 & !s10;
-- Node name is '~284~2'
-- Equation name is '~284~2', location is LC2_C12, type is buried.
-- synthesized logic cell
_LC2_C12 = LCELL( _EQ081);
_EQ081 = !_LC3_C9 & size2
# _LC3_C9 & !size2
# !_LC1_C9 & size3
# _LC1_C9 & !size3;
-- Node name is '~284~3'
-- Equation name is '~284~3', location is LC3_C12, type is buried.
-- synthesized logic cell
_LC3_C12 = LCELL( _EQ082);
_EQ082 = _LC5_C9
# _LC2_C12
# !_LC5_C11 & size6
# _LC5_C11 & !size6;
-- Node name is '~284~4'
-- Equation name is '~284~4', location is LC4_C12, type is buried.
-- synthesized logic cell
_LC4_C12 = LCELL( _EQ083);
_EQ083 = _LC7_C9 & size4 & s14
# !_LC7_C9 & size4 & !s14
# !_LC7_C9 & !size4 & s14
# _LC7_C9 & !size4 & !s14
# _LC3_C12;
-- Node name is '~284~5'
-- Equation name is '~284~5', location is LC7_C12, type is buried.
-- synthesized logic cell
_LC7_C12 = LCELL( _EQ084);
_EQ084 = _LC4_C12
# _LC5_C12 & size5 & s15
# !_LC5_C12 & size5 & !s15
# !_LC5_C12 & !size5 & s15
# _LC5_C12 & !size5 & !s15;
-- Node name is ':284'
-- Equation name is '_LC6_C12', type is buried
!_LC6_C12 = _LC6_C12~NOT;
_LC6_C12~NOT = LCELL( _EQ085);
_EQ085 = !_LC1_C1 & size8
# _LC1_C1 & !size8
# !_LC1_C12
# _LC7_C12;
-- Node name is ':292'
-- Equation name is '_LC1_C12', type is buried
!_LC1_C12 = _LC1_C12~NOT;
_LC1_C12~NOT = LCELL( _EQ086);
_EQ086 = _LC4_C11 & size7 & s17
# !_LC4_C11 & size7 & !s17
# !_LC4_C11 & !size7 & s17
# _LC4_C11 & !size7 & !s17;
-- Node name is ':306'
-- Equation name is '_LC5_C1', type is buried
_LC5_C1 = LCELL( _EQ087);
_EQ087 = !_LC6_C12 & !s17 & s18
# !_LC4_C11 & !_LC6_C12 & s18
# _LC4_C11 & !_LC6_C12 & s17 & !s18;
-- Node name is ':309'
-- Equation name is '_LC7_C11', type is buried
_LC7_C11 = LCELL( _EQ088);
_EQ088 = !_LC6_C12 & !s14 & s15
# !_LC6_C12 & !_LC7_C9 & s15
# !_LC6_C12 & _LC7_C9 & s14 & !s15;
-- Node name is ':310'
-- Equation name is '_LC6_C11', type is buried
_LC6_C11 = LCELL( _EQ089);
_EQ089 = !_LC6_C12 & !_LC7_C9 & s14
# !_LC6_C12 & _LC7_C9 & !s14;
-- Node name is ':313'
-- Equation name is '_LC4_C9', type is buried
_LC4_C9 = LCELL( _EQ090);
_EQ090 = !_LC6_C12 & s10 & !s11
# !_LC6_C12 & !s10 & s11;
-- Node name is '~325~1'
-- Equation name is '~325~1', location is LC3_C2, type is buried.
-- synthesized logic cell
_LC3_C2 = LCELL( _EQ091);
_EQ091 = _LC5_C11 & !_LC6_C12 & !size7
# _LC6_C12 & size7
# !_LC5_C11 & size7
# !_LC2_C2;
-- Node name is '~325~2'
-- Equation name is '~325~2', location is LC8_C2, type is buried.
-- synthesized logic cell
_LC8_C2 = LCELL( _EQ092);
_EQ092 = _LC1_C9 & !_LC6_C12 & !size4
# _LC6_C12 & size4
# !_LC1_C9 & size4
# _LC3_C2;
-- Node name is '~325~3'
-- Equation name is '~325~3', location is LC8_C11, type is buried.
-- synthesized logic cell
_LC8_C11 = LCELL( _EQ093);
_EQ093 = _LC6_C11 & !size5
# !_LC6_C11 & size5
# _LC4_C9 & !size2
# !_LC4_C9 & size2;
-- Node name is '~325~4'
-- Equation name is '~325~4', location is LC2_C1, type is buried.
-- synthesized logic cell
_LC2_C1 = LCELL( _EQ094);
_EQ094 = _LC8_C2
# _LC5_C1
# !_LC8_C1
# _LC8_C11;
-- Node name is ':325'
-- Equation name is '_LC7_C2', type is buried
!_LC7_C2 = _LC7_C2~NOT;
_LC7_C2~NOT = LCELL( _EQ095);
_EQ095 = _LC2_C1
# !_LC4_C2
# !_LC7_C11 & size6
# _LC7_C11 & !size6;
-- Node name is ':326'
-- Equation name is '_LC2_C2', type is buried
!_LC2_C2 = _LC2_C2~NOT;
_LC2_C2~NOT = LCELL( _EQ096);
_EQ096 = !_LC6_C12 & !size1 & !s10
# size1 & s10
# _LC6_C12 & size1;
-- Node name is ':328'
-- Equation name is '_LC4_C2', type is buried
!_LC4_C2 = _LC4_C2~NOT;
_LC4_C2~NOT = LCELL( _EQ097);
_EQ097 = _LC3_C9 & !_LC6_C12 & !size3
# _LC6_C12 & size3
# !_LC3_C9 & size3;
-- Node name is ':333'
-- Equation name is '_LC8_C1', type is buried
!_LC8_C1 = _LC8_C1~NOT;
_LC8_C1~NOT = LCELL( _EQ098);
_EQ098 = !_LC4_C11 & !_LC6_C12 & !size8 & s17
# _LC4_C11 & !_LC6_C12 & !size8 & !s17
# _LC4_C11 & size8 & s17
# !_LC4_C11 & size8 & !s17
# _LC6_C12 & size8;
-- Node name is ':347'
-- Equation name is '_LC6_C2', type is buried
_LC6_C2 = DFFE( _EQ099, GLOBAL(!clk), VCC, VCC, VCC);
_EQ099 = !_LC1_C8 & _LC6_C2 & !_LC7_C2
# !_LC1_C8 & _LC6_C12 & !_LC7_C2;
-- Node name is ':348'
-- Equation name is '_LC1_C2', type is buried
!_LC1_C2 = _LC1_C2~NOT;
_LC1_C2~NOT = LCELL( _EQ100);
_EQ100 = !_LC6_C2 & !_LC8_A2;
Project Information d:\2fsk\fpq.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,086K
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