ram_control_block.vhd

我自己写的vhdl程序

LIBRARY IEEE;
USE ieee.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;  -- add unsigned, signed
USE work.ALL; 


ENTITY rc IS
   PORT(
        x,y: IN STD_LOGIC_VECTOR( 5 DOWNTO 0);
        pen: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
        drawpixel, flushcache: IN STD_LOGIC;
        ack: OUT STD_LOGIC;
        clk,reset: IN STD_LOGIC;
     
        -- bus to VRAM
        vdin : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
        vdout : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
        vra : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
        vrw : OUT STD_LOGIC
           );
END rc;

ARCHITECTURE fsm OF rc IS   
   TYPE fsm IS (init, wordtransfer, comparison,changeaddr1,changeaddr2,writepixel);
   SIGNAL next_state, state :fsm;
   SIGNAL comp: STD_LOGIC;
   SIGNAL current_word_address,xy:STD_LOGIC_VECTOR(7 DOWNTO 0);
   SIGNAL stored_ram_word:STD_LOGIC_VECTOR(15 DOWNTO 0);
   SIGNAL counter:STD_LOGIC_VECTOR(2 DOWNTO 0);

BEGIN
    STATE_PROC:
    PROCESS(state,flushcache,comp,drawpixel,counter)
    BEGIN
        next_state <= state;
        CASE state is
            WHEN init => 
                IF flushcache ='1' THEN next_state <= wordtransfer;
                ELSIF drawpixel = '1' THEN next_state <= comparison;
                END IF;
            WHEN wordtransfer => 
                IF counter="000"
                THEN next_state <= init;
                END IF;
            WHEN comparison => 
               IF comp ='0' THEN next_state <= changeaddr1; 
               ELSE next_state <= writepixel;
               END IF;
            WHEN changeaddr1 =>
               IF counter="000"
               THEN 
               next_state <= changeaddr2;
               END IF;
           WHEN changeaddr2 => 
               IF counter="000"
               THEN 
               next_state <= writepixel;
               END IF;
            WHEN writepixel => 
               IF flushcache ='1' THEN next_state <= init;
               ELSIF drawpixel = '1' THEN next_state <= comparison;
               ELSE 
               next_state <= init;
               END IF; 
        END CASE;     
    END PROCESS STATE_PROC;
    
    SS_PROC:
    PROCESS
    BEGIN
        WAIT UNTIL clk'EVENT and clk='1';
        state<=next_state;
        IF reset='1' THEN
            state<=init;
        END IF;
    END PROCESS SS_PROC;       
            
    MAIN_PROC:
    PROCESS(next_state,x,y)----,x,y,stored_ram_word,current_word_address)     
    BEGIN 
        xy<= x(5 DOWNTO 2)&y(5 DOWNTO 2);
        CASE (next_state) IS
            WHEN init => 
                ack <='1';
                vrw <='0';
            WHEN wordtransfer =>

                ack <='1';
                vrw <='1';
            WHEN comparison =>
                ack <='0';
                vrw <='0';
            WHEN changeaddr1 =>
                ack<= '0';
                vrw <='1';
            WHEN changeaddr2 =>
                ack<= '0';
                vrw <='0';
            WHEN writepixel =>
                ack<= '1';
                vrw <='0';
       END CASE; 
    END PROCESS MAIN_PROC;
  
    REG_PROC:
    PROCESS    
    BEGIN    
        WAIT UNTIL clk'EVENT and clk='1';
        IF reset = '1' 
        THEN current_word_address <= (OTHERS=>'0');
              vdin <= (OTHERS=>'0');
              stored_ram_word <= (OTHERS=>'0');
              vra<= (OTHERS=>'0');
        END IF; 
            
        CASE next_state is
            WHEN wordtransfer =>
                counter<="001";
                IF  counter/="000"
                THEN counter<= unsigned(counter)-1;
                END IF;
                vdin <= stored_ram_word;
            WHEN comparison =>
                IF xy = current_word_address 
                THEN comp <='1';
                ELSE comp <='0';
                END IF;
            WHEN changeaddr1 =>
                counter<="001";
                IF state=changeaddr1 and counter /="000"
                THEN counter<= unsigned(counter) -1;
                END IF; 
                vdin <= stored_ram_word; 
            WHEN changeaddr2 =>
                counter<="100";
                IF state=changeaddr2 and counter/="000"
                THEN counter<= unsigned(counter) -1;
                END IF;
                current_word_address <= x(5 DOWNTO 2)&y(5 DOWNTO 2);
                vra <= current_word_address; 
                stored_ram_word <=vdout;   
            WHEN writepixel =>
               CASE pen IS
                    WHEN "00"=> 
                        stored_ram_word(conv_integer(unsigned(x(1 DOWNTO 0)&y(1 DOWNTO 0))))<= '0';
                    WHEN "01"=> 
                        stored_ram_word(conv_integer(unsigned(x(1 DOWNTO 0)&y(1 DOWNTO 0))))<= '1';
                    WHEN "10"=> 
                        stored_ram_word(conv_integer(unsigned(x(1 DOWNTO 0)&y(1 DOWNTO 0))))<= not stored_ram_word(conv_integer(unsigned(x(1 DOWNTO 0)&y(1 DOWNTO 0))));
                    WHEN OTHERS =>null;
                END CASE;
            WHEN OTHERS =>null;   
        END CASE; 
    END PROCESS REG_PROC;    
 END ARCHITECTURE fsm;