vdp.vhd

来自「我自己写的vhdl程序」· VHDL 代码 · 共 64 行

-- top-level Vector Display Processor
-- this file is fully synthesisable
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE work.vdp_pack.ALL;
USE work.ALL;

ENTITY vdp IS
   PORT(
      clk: IN std_logic;
      reset: IN std_logic;
      -- bus from host
      hdb      : IN  STD_LOGIC_VECTOR( 15 DOWNTO 0);
      dav      : IN  STD_LOGIC;
      hdb_busy : OUT STD_LOGIC;

      -- bus to VRAM
      vdin   : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
      vdout  : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
      vaddr  : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
      vwrite : OUT STD_LOGIC
      );
END vdp;


ARCHITECTURE rtl OF vdp IS
    signal pen:std_logic_vector(1 downto 0);
    signal drawpixel,fcache,ack:std_logic;
    signal x,y:std_logic_vector(5 downto 0);
    
BEGIN
    DB1:ENTITY DB PORT MAP(
       reset=>reset,
       pen=>pen,
       x=>x,
       y=>y,
       drawpixel=> drawpixel,
       flush=>fcache,
       ack=>ack,
       hdb=>hdb,
       dav=>dav,
       clk=>clk,
       hdb_busy=>hdb_busy
       );   
    
    
    RC1:ENTITY rc PORT MAP(
       clk=>clk,
       reset=>reset,
       vdin=>vdin,
       vdout=>vdout,
       vra=>vaddr,
       vrw=>vwrite,
       pen=>pen,
       x=>x,
       y=>y,
       drawpixel=> drawpixel,
       flushcache=>fcache,
       ack=>ack
       );

END rtl;