draw_block.vhd

我自己写的vhdl程序

LIBRARY IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

ENTITY DB IS
    PORT(
        hdb: in std_logic_vector(15 downto 0);
        ack,dav,clk,reset: in std_logic;
        hdb_busy,drawpixel,flush: out std_logic;
        x,y: out std_logic_vector(5 downto 0);
        pen: out std_logic_vector(1 downto 0)
        );
    END DB;
    
architecture dflow of DB is
    TYPE FSM1 IS (initial,wcomm,tcomm,sline,dline,cscrean,fcache,finish);
    signal next_state,state:FSM1;
    signal x_current,y_current,x_old,y_old:std_logic_vector(5 downto 0);
    signal d_y,d_x,x_oldc,y_oldc,d_x_i,d_y_i,x_oldco,y_oldco:std_logic_vector(7 downto 0);
    signal hdb_hold:std_logic_vector(15 downto 0);
    signal done,a:std_logic;
    signal oct:std_logic_vector(2 downto 0);
    signal err2,err1:signed(7 downto 0);
    BEGIN
        d_x_i<=signed("00"&x_current)-signed(x_oldc);
        d_y_i<=signed("00"&y_current)-signed(y_oldc);  
        
        col:process(d_x_i,d_y_i,err1,err2,x_oldc,y_oldc,a)
        begin  
            if signed(d_x_i)>0 then oct(2)<='0';else oct(2)<='1';end if;
            if signed(d_y_i)>0 then oct(1)<='0';else oct(1)<='1';end if;
            if abs(conv_integer(signed(d_x_i)))>abs(conv_integer(signed(d_y_i)))then oct(0)<='0';else oct(0)<='1';end if;
            if abs(conv_integer(signed(err1)))<=abs(conv_integer(signed(err2))) then a<='0'; else a<='1'; end if;
            
			case oct is 
                 when"000"=>
	                err1<=signed(d_y_i)-signed(d_x_i);
                   err2<=signed(d_y_i);
                   case a is 
                   when '0'=>
    		             x_oldco<=unsigned(x_oldc)+1;
              		   y_oldco<=unsigned(y_oldc)+1;
          		       when others=>
              		   x_oldco<=unsigned(x_oldc)+1;
              		   y_oldco<=y_oldc;
                   end case;
                   
                when"001"=>
                   err1<=-signed(d_x_i);
                   err2<=signed(d_y_i)-signed(d_x_i);
                   case a is 
                   when '0'=>
        		         x_oldco<=x_oldc;
              	    y_oldco<=unsigned(y_oldc)+1; 
              		   when others=>
              		   x_oldco<=unsigned(x_oldc)+1;
              		   y_oldco<=unsigned(y_oldc)+1; 
                   end case;
        
                when"101"=>
	                err1<=-signed(d_y_i) - signed(d_x_i) ;
                   err2<=-signed(d_x_i);
                   case a is 
                   when '0'=>
        		         x_oldco<=unsigned(x_oldc)-1;
              	    y_oldco<=unsigned(y_oldc)+1;	 
              	    when others=> 
              		   x_oldco<=x_oldc;
              		   y_oldco<=unsigned(y_oldc)+1; 
                   end case;

                when"100"=>
	                err1<=-signed(d_y_i);
                   err2<=-signed(d_y_i) - signed(d_x_i);
                   case a is 
                   when '0'=>
        		         x_oldco<=unsigned(x_oldc)-1;
        	          y_oldco<=y_oldc;	
        	          when others=>	
              		   x_oldco<=unsigned(x_oldc)-1;
              		   y_oldco<=unsigned(y_oldc)+1;	 
                   end case;

               when"110"=>
	               err1<=signed(d_x_i) - signed(d_y_i);
                  err2<=-signed(d_y_i);
                  case a is 
                  when '0'=>
  		            x_oldco<=unsigned(x_oldc)-1;
     	            y_oldco<=unsigned(y_oldc)-1;	 
              		  when others=>
              		  x_oldco<=unsigned(x_oldc)-1;
              		  y_oldco<=y_oldc;
                  end case;

               when"111"=>
	               err1<=signed(d_x_i); 
                  err2<=signed(d_x_i)-signed(d_y_i);
                  case a is 
                  when '0'=>
  		            x_oldco<=x_oldc;
           	      y_oldco<=unsigned(y_oldc)-1;	
           	      when others=>	
        		        x_oldco<=unsigned(x_oldc)-1;
              		  y_oldco<=unsigned(y_oldc)-1;	
                  end case;

               when"011"=>
	               err1<=signed(d_y_i) + signed(d_x_i);
                  err2<=signed(d_x_i);
                  case a is 
                  when '0'=>
  		            x_oldco<=unsigned(x_oldc)+1;
              	   y_oldco<=unsigned(y_oldc)-1;
              	   when others=>	
              		  x_oldco<=x_oldc;
              		  y_oldco<=unsigned(y_oldc)-1;
                  end case;

               when"010"=>
                  err1<=signed(d_y_i);
                  err2<=signed(d_y_i) + signed(d_x_i);
                  case a is 
                  when '0'=>
        		        x_oldco<=unsigned(x_oldc)+1;
        	         y_oldco<=y_oldc;	
        	         when others=>	
           		     x_oldco<=unsigned(x_oldc)+1;
           		     y_oldco<=unsigned(y_oldc)-1;	
                  end case;
               
               when others=>null; 
                   end case;
               end process col; 
        FMSF:PROCESS(state,reset,dav,hdb_hold,done)
           BEGIN
               next_state<=state;
               if reset='1' then
                   next_state<=initial;
               else
               case state is
                   when initial=>  next_state<=wcomm;
                   when wcomm=> IF dav='1' then  next_state<=tcomm;
                                   END IF;
                   when tcomm=>
                       case hdb_hold(15 downto 14) is
                       when "00" =>
                           next_state<=sline;
                       when "01" =>
                           next_state<=dline;
                       when "10" =>
                           next_state<=cscrean;
                       when "11" =>
                           next_state<=fcache;
                       when others=> null;
                       end case;
                   when sline=> next_state<=wcomm;
                   when dline=> if done='1' then next_state<=wcomm;
                                              else next_state<=dline;end if;
                   when cscrean=> if done = '1' then next_state<=wcomm;
                                              else next_state<=cscrean;end if;
                   when fcache=> if done='1' then next_state<=finish;
                                              else next_state<=fcache;end if;
                   when finish=>next_state<=wcomm;            
               end case;
               end if;
           END PROCESS FMSF;
           
           RE:process--reset process
           begin 
               wait until clk'EVENT and clk='1';
               state<=next_state;
           END process RE;
        
        p_test:process
        begin 
            wait until clk'EVENT and clk='1';
            case state is
            when initial =>
                drawpixel<='0';
                flush<='0';
                x_old<=(others=>'0');
				    y_old<=(others=>'0');
                x_oldc<=(others=>'0');
                y_oldc<=(others=>'0');
                x_current<=(others=>'0');
                y_current<=(others=>'0');
            
        
             when wcomm =>
                 drawpixel<='0';
                 flush<='0';	  
                 d_x<=(others=>'0');
                 d_y<=(others=>'0');
                 x_old<=x_current;
                 y_old<=y_current;
                 done<='0';
             
    when tcomm =>
          x_current<=hdb_hold(13 downto 8);
          y_current<=hdb_hold(7 downto 2);
          x_oldc<="00"&x_old;
          y_oldc<="00"&y_old;

    when sline =>
          x_old<=x_current;
	       y_old<=y_current;
	       
	       
     when dline =>
           if ack='1' then
               d_x<=d_x_i;
               d_y<=d_y_i;
               x_oldc<=x_oldco;
               y_oldc<=y_oldco;
               pen<=hdb_hold(1 downto 0);
               drawpixel<='1';
               x<=std_logic_vector(x_oldc(5 downto 0));
               y<=std_logic_vector(y_oldc(5 downto 0));
               if signed(x_oldc(5 downto 0))=signed(x_current) and signed(y_oldc(5 downto 0))=signed(y_current) then 
               done<='1'; else done<='0';end if; 
               else 
                  null;
               end if;        
      
    when cscrean =>
        drawpixel<='1';
        d_x<=signed("00"&x_current)-signed(x_oldc);
        d_y<=signed("00"&y_current)-signed(y_oldc);
        if signed(x_oldc(5 downto 0))=signed(x_current) and signed(y_oldc(5 downto 0))=signed(y_current) then 
        done<='1'; else done<='0';end if;
        if ack ='1' then
        x<=std_logic_vector(x_oldc(5 downto 0));
        y<=std_logic_vector(y_oldc(5 downto 0));        
        if signed(d_y)>0 then
            if signed(d_x)>0 then
               x_oldc<=signed(x_oldc)+1;
               elsif signed(d_x)<0 then
               x_oldc<=signed(x_oldc)-1;
            else
               y_oldc<=signed(y_oldc)+1;
               x_oldc<="00"&x_old;
            end if;
            elsif signed(d_y)<0 then
                  if signed(d_x)>0 then
                     x_oldc<=signed(x_oldc)+1;
                     elsif signed(d_x)<0 then
                     x_oldc<=signed(x_oldc)-1;
                     else
                     y_oldc<=signed(y_oldc)-1;
                     x_oldc<="00"&x_old;
                  end if;
            else
                  if signed(d_x)>0 then
                     x_oldc<=signed(x_oldc)+1;
                     elsif signed(d_x)<0 then
                     x_oldc<=signed(x_oldc)-1;
                  	else
                     null;
                  end if;
            end if;
            else null;
        end if;
       
    when fcache =>
        if ack='1'then 
        x<=x_current;
        y<=y_current;
        flush<='1';
        done<='1';
        else
           null;
       end if;
       when others=>null;

    end case;
end process p_test;

p_hdb:process
begin
    wait until clk'EVENT and clk='1';
    case state is 
    when initial=> hdb_busy<='0';
    when wcomm=> if dav='1' then hdb_busy<='1'; hdb_hold<=hdb;else hdb_busy<='0';end if;
    when others=> hdb_busy<='1';
    end case;
end process p_hdb;

end dflow;