fifo_v.npl

来自「fifo verilog hdl 源程序」· NPL 代码 · 共 40 行

JDF G
// Converted from an earlier version by Project Navigator version 5
PROJECT fifoctrl_v
DESIGN fifo_v Normal
DEVFAM virtex
DEVFAMTIME 1016217226
DEVICE xcv50
DEVICETIME 1016217226
DEVPKG bg256
DEVPKGTIME 1016217226
DEVSPEED -6
DEVSPEEDTIME 1016217226
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL Verilog
GENERATEDSIMULATIONMODELTIME 0
STIMULUS fifoctrl_ic_tb2_timing.tf Normal
STIMULUS fifoctrl_cc_tb.tf Normal
STIMULUS fifoctrl_cc_tb_timing.tf Normal
STIMULUS fifoctrl_ic_tb1.tf Normal
STIMULUS fifoctrl_ic_tb2.tf Normal
STIMULUS fifoctrl_ic_tb1_timing.tf Normal
DOCUMENT readme
MODULE fifoctlr_ic.v
MODSTYLE xor4_p Normal
MODSTYLE muxor_p Normal
MODSTYLE fifoctlr_ic Normal
MODSTYLE xor5_p Normal
MODULE fifoctlr_cc.v
MODSTYLE and4b1_p Normal
MODSTYLE and4b4_p Normal
MODSTYLE fifoctlr_cc Normal
MODSTYLE and4_p Normal
[STRATEGY-LIST]
Normal=True