test_cpu.v

来自「一个小单片机的verilog源代码, 包含说明文档」· Verilog 代码 · 共 41 行

module test;

    reg [3:0] op;
    reg [7:0] in;
    reg [11:0] mem[(`index-1):0],temp;
    reg       clk;
    wire [7:0] out;
    integer  i;

    cpu U0(op,in,clk,out,overflow);

    always #(`cycle/2) clk=~clk;

    initial
      begin
        clk=1;
        $readmemb("in.dat",mem);   //read test pattern
        
        for (i=0;i<`index;i=i+1) #(`cycle)
          begin
            temp=mem[i];
            op=temp[11:8];
            in=temp[7:0];
          end
      end

   initial
     begin
       $monitor("%d %b %b %b   %b %b",i,clk,op,in,out,overflow);
       #(`cycle*(`index+2)) $stop;
       #1 $finish;
     end

  initial 
    begin 
//      $gr_waves("CLK",clk,"OP",op,"in",in,"out",out,"overflow",overflow);
      $fsdbDumpvars;
      #(`cycle*(`index+2)) $stop;
      #1 $finish;
    end 
endmodule