cpu.v

一个小单片机的verilog源代码, 包含说明文档

`define  mux_2_1_delay      2
`define  mux_4_1_delay      2
`define  adder8_delay       7
`define  posedge_reg_delay  1.4
`define  negedge_reg_delay  1.4
`define  op_delay           2
`define  ram64x8_delay      5
`define  low_dff_delay      1.4
`define  index             23   
`define  cycle             20   //clk= 50M Hz
`timescale 1ns/100ps

module mux_2_1(a,b,sel,out);

    input  [7:0]a,b;
    input  sel;
    output [7:0] out;
    wire   [7:0] out;

    assign #`mux_2_1_delay out=(sel==0)?a:b;

endmodule

module mux_4_1(a0,a1,a2,a3,sel,out);

    input  [7:0] a0,a1,a2,a3;
    input  [1:0] sel;
    output [7:0] out;
    wire   [7:0] out;

    assign #`mux_4_1_delay out=(sel==2'b00)?a0:
                               (sel==2'b01)?a1:
                               (sel==2'b10)?a2:
                                            a3;

endmodule

module posedge_reg_8(in,En,clk,out);

    input  [7:0] in;
    input  En,clk;
    output [7:0] out;
    reg [7:0] out;

    always @(posedge clk) #`posedge_reg_delay
      if(En)
         out=in;

endmodule

module negedge_reg_1(in,clk,out);

    input  in;
    input  clk;
    output out;
    reg    out;

    always @(negedge clk) #`posedge_reg_delay
      out=in;

endmodule

module negedge_reg_8(in,En,clk,out);

    input  [7:0] in;
    input  En,clk;
    output [7:0] out;
    reg [7:0] out;
    always @(negedge clk) #`negedge_reg_delay
      if(En)
         out=in;

endmodule

module low_dff(in,clk,out);

    input  [7:0]  in;
    input  clk;
    output [7:0] out;
    reg [7:0] out;

    always @(in or clk) #`low_dff_delay
      if(clk==1'b0)
        out=in;

endmodule

// 1'complement adder//
module adder8(a,b,sel,cin,sum,overflow);

    input [7:0] a,b;
    input sel,cin;
    output [7:0] sum;
    output overflow;

    reg [7:0] sum,b_temp;
    reg cout,overflow;

    always @(a or b or cin) #`adder8_delay
      begin
        if (!sel)
          b_temp=b;
        else
          b_temp=~b;
      
        {cout,sum}=a+b_temp+cin;
        overflow=(a[7]&b_temp[7]&~sum[7])|(~a[7]&~b_temp[7]&sum[7]);
      end

endmodule

module  op_decoder(op,
                   Input_sel,Ram_sel,En_A,En_B,En_C,A_sel,
                   B_sel,C_sel,ALU_sel,Cin,Write,Output_sel);

    input  [3:0] op;
    output [1:0] B_sel;
    output Input_sel,Ram_sel,En_A,En_B,En_C,A_sel,
           C_sel,ALU_sel,Cin,Write,Output_sel;

    reg    [1:0] B_sel;
    reg    Input_sel,Ram_sel,En_A,En_B,En_C,A_sel,
           C_sel,ALU_sel,Cin,Write,Output_sel;
    wire   [3:0] _op;

    assign _op=~op;

    always  @(op) #`op_delay
      fork
        Input_sel = _op[3] | _op[2] | (_op[1]&_op[0]) | (op[1]&op[0]) ;
        Ram_sel = op[0] ;
        En_A = (_op[3]&op[2]&op[1]&_op[0]) | (op[3]&op[2]&op[0]) ;
        En_B = (op[2]&op[1]&op[0]) | (op[3]&op[2]&op[1]) ;
        En_C = (_op[3]&_op[1]) | (_op[3]&_op[2]) |  
               (_op[2]&op[1]&_op[0]) ; 
        A_sel = (_op[1]&_op[0]) | _op[2] ;
        B_sel[1] = op[1] ;
        B_sel[0] = (_op[1]&_op[0]) | (_op[2]&op[0]) ;
        C_sel = op[3] ;
        ALU_sel = _op[1]&op[0] ;
        Cin = (_op[1]&op[0]) | (_op[3]&op[2]) ;
        Write = op[3]&_op[2]&_op[1] ;
        Output_sel = op[2] ;
      join

endmodule

module ram64x8(input_data,addr,write,clk,output_data);

    input  [7:0] input_data;
    input  [5:0] addr;
    input  write,clk;
    output [7:0] output_data;

    reg [7:0] output_data;
    reg [7:0] ram[63:0];

    always@(negedge clk) #`ram64x8_delay
      if(write)
        begin
            ram[addr]=input_data;
          output_data=input_data;
        end
      else
        output_data=ram[addr];

endmodule

module cpu(op,in,clk,out,overflow);

    input  [3:0] op;
    input  [7:0] in;
    input        clk;
    output [7:0] out;
    output       overflow;
    wire   [7:0] reg_c_out,input_mux_out,ram_mux_out,reg_a_out,reg_b_out,
                 ram_out,alu_a_mux_out,alu_b_mux_out,alu_out,dff_alu_out,
                 dff_ram_out,reg_c_mux_out;
    wire         Input_sel,Ram_sel,En_A,En_B,En_C,En_C_temp,A_sel,
                 C_sel,C_sel_temp,ALU_sel,Cin,Write,Write_temp,Output_sel;
    wire   [1:0] B_sel;


    mux_2_1       Input_mux  (reg_c_out,in,Input_sel,input_mux_out);
    mux_2_1       Ram_mux    (in,reg_c_out,Ram_sel,ram_mux_out);
    negedge_reg_8 Reg_A      (input_mux_out,En_A,clk,reg_a_out);
    negedge_reg_8 Reg_B      (input_mux_out,En_B,clk,reg_b_out);
    ram64x8       Ram        (ram_mux_out,reg_b_out[5:0],Write,clk,ram_out);
    mux_2_1       ALU_A_mux  (8'h00,reg_a_out,A_sel,alu_a_mux_out);
    mux_4_1       ALU_B_mux  (reg_a_out,reg_b_out,8'h01,8'hff,B_sel,
                              alu_b_mux_out);
    adder8        ALU        (alu_a_mux_out,alu_b_mux_out,ALU_sel,Cin,alu_out,
                              overflow);
    low_dff       DFF_ALU    (alu_out,clk,dff_alu_out);
    low_dff       DFF_Ram    (ram_out,clk,dff_ram_out);
    mux_2_1       Reg_C_mux  (dff_alu_out,dff_ram_out,C_sel,reg_c_mux_out);
    posedge_reg_8 Reg_C      (reg_c_mux_out,En_C,clk,reg_c_out);
    mux_2_1       Output_mux (reg_c_out,ram_out,Output_sel,out);

    op_decoder    Controll   (op,
                              Input_sel,Ram_sel,En_A,En_B,En_C_temp,A_sel,B_sel,
                              C_sel_temp,ALU_sel,Cin,Write_temp,Output_sel);

    negedge_reg_1 U0         (En_C_temp,clk,En_C);
    negedge_reg_1 U1         (C_sel_temp,clk,C_sel);
    and           U2         (Write,Write_temp,~clk);

endmodule