speakera.vhd

来自「基于max—plus2开发环境」· VHDL 代码 · 共 38 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SPEAKERA IS
  PORT(CLK:IN STD_LOGIC;
       TONE:IN INTEGER RANGE 0 TO 16#7FF#;
       SPKS:OUT STD_LOGIC);
END SPEAKERA;
ARCHITECTURE behav OF SPEAKERA IS 
  SIGNAL PRECLK,FULLSPKS:STD_LOGIC;
  BEGIN
DIVIDECLK:PROCESS(CLK)
  VARIABLE COUNT4:INTEGER RANGE 0 TO 15;
 BEGIN
  PRECLK<='0';
  IF COUNT4>11 THEN PRECLK<='1';COUNT4:=0;
  ELSIF CLK'EVENT AND CLK='1' THEN COUNT4:=COUNT4+1;
  END IF;
 END PROCESS;
GENSPKS:PROCESS(PRECLK,TONE)
  VARIABLE COUNT11:INTEGER RANGE 0 TO 16#7FF#;
 BEGIN
IF PRECLK'EVENT AND PRECLK='1' THEN
  IF COUNT11=16#7FF# THEN COUNT11:=TONE;FULLSPKS<='1';
    ELSE COUNT11:=COUNT11+1;FULLSPKS<='0';
  END IF;
END IF;
END PROCESS;
DELAYSPKS:PROCESS(FULLSPKS)
  VARIABLE COUNT2:STD_LOGIC;
    BEGIN
  IF FULLSPKS'EVENT AND FULLSPKS='1' THEN COUNT2:=NOT COUNT2;
    IF COUNT2='1' THEN SPKS<='1';
    ELSE SPKS<='0';
    END IF;
  END IF;
END PROCESS;
END behav;