songer.vhd

来自「基于max—plus2开发环境」· VHDL 代码 · 共 35 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SONGER IS
  PORT(CLK12MHZ:IN STD_LOGIC;
       CLK8HZ:IN STD_LOGIC;
       CODE1:OUT INTEGER RANGE 0 TO 15;
       HIGH1:OUT STD_LOGIC;
       SPKOUT: OUT STD_LOGIC);
END ENTITY SONGER;
ARCHITECTURE one OF SONGER IS
     COMPONENT NOTETABS
       PORT(CLK:IN STD_LOGIC;
            TONEINDEX:OUT INTEGER RANGE 0 TO 15);
      END COMPONENT;
     COMPONENT TONETABA
       PORT(  INDEX:  IN INTEGER RANGE 0 TO 15;
              CODE: OUT  INTEGER RANGE 0 TO 15;
              HIGH:OUT STD_LOGIC;
              TONE:OUT INTEGER RANGE 0 TO 16#7FF#);
       END COMPONENT;
     COMPONENT SPEAKERA
          PORT(  CLK: IN STD_LOGIC;
                 TONE:IN INTEGER RANGE 0 TO 16#7FF#;
                 SPKS: OUT STD_LOGIC);
     END COMPONENT;
 SIGNAL TONE:INTEGER RANGE 0 TO 16#7FF#;
 SIGNAL TONEINDEX:INTEGER RANGE 0 TO 15;
BEGIN
U1:NOTETABS PORT MAP(CLK=>CLK8HZ,TONEINDEX=>TONEINDEX);
U2:TONETABA PORT MAP(INDEX=>TONEINDEX,TONE=>TONE,CODE=>CODE1,HIGH=>HIGH1);
U3:SPEAKERA PORT MAP(CLK=>CLK12MHZ,TONE=>TONE,SPKS=>SPKOUT);
END;