📄 speakera.rpt
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Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\eda6\qj\speakera.rpt
speakera
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 16 :27
INPUT 4 CLK
DFF 2 FULLSPKS
Device-Specific Information: d:\eda6\qj\speakera.rpt
speakera
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 16 :27
Device-Specific Information: d:\eda6\qj\speakera.rpt
speakera
** EQUATIONS **
CLK : INPUT;
TONE0 : INPUT;
TONE1 : INPUT;
TONE2 : INPUT;
TONE3 : INPUT;
TONE4 : INPUT;
TONE5 : INPUT;
TONE6 : INPUT;
TONE7 : INPUT;
TONE8 : INPUT;
TONE9 : INPUT;
TONE10 : INPUT;
-- Node name is ':284' = 'COUNT2'
-- Equation name is 'COUNT2', location is LC8_B13, type is buried.
COUNT2 = DFFE(!COUNT2, FULLSPKS, VCC, VCC, VCC);
-- Node name is ':21' = 'COUNT40'
-- Equation name is 'COUNT40', location is LC5_B14, type is buried.
COUNT40 = DFFE(!COUNT40, GLOBAL( CLK), !_LC1_B14, VCC, VCC);
-- Node name is ':20' = 'COUNT41'
-- Equation name is 'COUNT41', location is LC4_B14, type is buried.
COUNT41 = DFFE( _EQ001, GLOBAL( CLK), !_LC1_B14, VCC, VCC);
_EQ001 = COUNT40 & !COUNT41
# !COUNT40 & COUNT41;
-- Node name is ':19' = 'COUNT42'
-- Equation name is 'COUNT42', location is LC3_B14, type is buried.
COUNT42 = DFFE( _EQ002, GLOBAL( CLK), !_LC1_B14, VCC, VCC);
_EQ002 = !COUNT40 & COUNT42
# !COUNT41 & COUNT42
# COUNT40 & COUNT41 & !COUNT42;
-- Node name is ':18' = 'COUNT43'
-- Equation name is 'COUNT43', location is LC2_B14, type is buried.
COUNT43 = DFFE( _EQ003, GLOBAL( CLK), !_LC1_B14, VCC, VCC);
_EQ003 = !COUNT42 & COUNT43
# !COUNT40 & COUNT43
# !COUNT41 & COUNT43
# COUNT40 & COUNT41 & COUNT42 & !COUNT43;
-- Node name is ':92' = 'COUNT110'
-- Equation name is 'COUNT110', location is LC1_B17, type is buried.
COUNT110 = DFFE( _EQ004, _LC1_B14, VCC, VCC, VCC);
_EQ004 = !COUNT110
# _LC2_B13 & TONE0;
-- Node name is ':91' = 'COUNT111'
-- Equation name is 'COUNT111', location is LC4_B16, type is buried.
COUNT111 = DFFE( _EQ005, _LC1_B14, VCC, VCC, VCC);
_EQ005 = COUNT110 & !COUNT111 & !_LC2_B13
# !COUNT110 & COUNT111 & !_LC2_B13
# _LC2_B13 & TONE1;
-- Node name is ':90' = 'COUNT112'
-- Equation name is 'COUNT112', location is LC3_B16, type is buried.
COUNT112 = DFFE( _EQ006, _LC1_B14, VCC, VCC, VCC);
_EQ006 = COUNT112 & !_LC2_B13 & !_LC7_B16
# !COUNT112 & !_LC2_B13 & _LC7_B16
# _LC2_B13 & TONE2;
-- Node name is ':89' = 'COUNT113'
-- Equation name is 'COUNT113', location is LC2_B16, type is buried.
COUNT113 = DFFE( _EQ007, _LC1_B14, VCC, VCC, VCC);
_EQ007 = COUNT113 & !_LC2_B13 & !_LC6_B16
# !COUNT113 & !_LC2_B13 & _LC6_B16
# _LC2_B13 & TONE3;
-- Node name is ':88' = 'COUNT114'
-- Equation name is 'COUNT114', location is LC1_B16, type is buried.
COUNT114 = DFFE( _EQ008, _LC1_B14, VCC, VCC, VCC);
_EQ008 = COUNT114 & !_LC2_B13 & !_LC5_B16
# !COUNT114 & !_LC2_B13 & _LC5_B16
# _LC2_B13 & TONE4;
-- Node name is ':87' = 'COUNT115'
-- Equation name is 'COUNT115', location is LC4_B15, type is buried.
COUNT115 = DFFE( _EQ009, _LC1_B14, VCC, VCC, VCC);
_EQ009 = COUNT115 & !_LC2_B13 & !_LC8_B16
# !COUNT115 & !_LC2_B13 & _LC8_B16
# _LC2_B13 & TONE5;
-- Node name is ':86' = 'COUNT116'
-- Equation name is 'COUNT116', location is LC3_B15, type is buried.
COUNT116 = DFFE( _EQ010, _LC1_B14, VCC, VCC, VCC);
_EQ010 = COUNT116 & !_LC2_B13 & !_LC6_B15
# !COUNT116 & !_LC2_B13 & _LC6_B15
# _LC2_B13 & TONE6;
-- Node name is ':85' = 'COUNT117'
-- Equation name is 'COUNT117', location is LC2_B15, type is buried.
COUNT117 = DFFE( _EQ011, _LC1_B14, VCC, VCC, VCC);
_EQ011 = COUNT117 & !_LC2_B13 & !_LC5_B15
# !COUNT117 & !_LC2_B13 & _LC5_B15
# _LC2_B13 & TONE7;
-- Node name is ':84' = 'COUNT118'
-- Equation name is 'COUNT118', location is LC3_B13, type is buried.
COUNT118 = DFFE( _EQ012, _LC1_B14, VCC, VCC, VCC);
_EQ012 = COUNT118 & !_LC1_B15 & !_LC2_B13
# !COUNT118 & _LC1_B15 & !_LC2_B13
# _LC2_B13 & TONE8;
-- Node name is ':83' = 'COUNT119'
-- Equation name is 'COUNT119', location is LC1_B13, type is buried.
COUNT119 = DFFE( _EQ013, _LC1_B14, VCC, VCC, VCC);
_EQ013 = COUNT119 & !_LC2_B13 & !_LC6_B13
# !COUNT119 & !_LC2_B13 & _LC6_B13
# _LC2_B13 & TONE9;
-- Node name is ':82' = 'COUNT1110'
-- Equation name is 'COUNT1110', location is LC5_B13, type is buried.
COUNT1110 = DFFE( _EQ014, _LC1_B14, VCC, VCC, VCC);
_EQ014 = !COUNT119 & COUNT1110
# COUNT1110 & !_LC6_B13
# COUNT119 & !COUNT1110 & _LC6_B13
# COUNT1110 & TONE10;
-- Node name is ':16' = 'FULLSPKS'
-- Equation name is 'FULLSPKS', location is LC7_B13, type is buried.
FULLSPKS = DFFE( _EQ015, _LC1_B14, VCC, VCC, VCC);
_EQ015 = COUNT118 & COUNT119 & COUNT1110 & _LC1_B15;
-- Node name is 'SPKS'
-- Equation name is 'SPKS', type is output
SPKS = _LC4_B13;
-- Node name is '|LPM_ADD_SUB:166|addcore:adder|:87' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B16', type is buried
_LC7_B16 = LCELL( _EQ016);
_EQ016 = COUNT110 & COUNT111;
-- Node name is '|LPM_ADD_SUB:166|addcore:adder|:91' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B16', type is buried
_LC6_B16 = LCELL( _EQ017);
_EQ017 = COUNT112 & _LC7_B16;
-- Node name is '|LPM_ADD_SUB:166|addcore:adder|:95' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B16', type is buried
_LC5_B16 = LCELL( _EQ018);
_EQ018 = COUNT113 & _LC6_B16;
-- Node name is '|LPM_ADD_SUB:166|addcore:adder|:99' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B16', type is buried
_LC8_B16 = LCELL( _EQ019);
_EQ019 = COUNT114 & _LC5_B16;
-- Node name is '|LPM_ADD_SUB:166|addcore:adder|:103' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B15', type is buried
_LC6_B15 = LCELL( _EQ020);
_EQ020 = COUNT115 & _LC8_B16;
-- Node name is '|LPM_ADD_SUB:166|addcore:adder|:107' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B15', type is buried
_LC5_B15 = LCELL( _EQ021);
_EQ021 = COUNT116 & _LC6_B15;
-- Node name is '|LPM_ADD_SUB:166|addcore:adder|:111' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B15', type is buried
_LC1_B15 = LCELL( _EQ022);
_EQ022 = COUNT117 & _LC5_B15;
-- Node name is '|LPM_ADD_SUB:166|addcore:adder|:115' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B13', type is buried
_LC6_B13 = LCELL( _EQ023);
_EQ023 = COUNT118 & _LC1_B15;
-- Node name is ':13'
-- Equation name is '_LC4_B13', type is buried
_LC4_B13 = DFFE(!COUNT2, FULLSPKS, VCC, VCC, VCC);
-- Node name is ':27'
-- Equation name is '_LC1_B14', type is buried
_LC1_B14 = LCELL( _EQ024);
_EQ024 = COUNT42 & COUNT43;
-- Node name is ':107'
-- Equation name is '_LC2_B13', type is buried
_LC2_B13 = LCELL( _EQ025);
_EQ025 = COUNT119 & COUNT1110 & _LC6_B13;
Project Information d:\eda6\qj\speakera.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = off
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 11,030K
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