pwmnios.vhd

niosPWM可以在SOPC builder中实现PWM功能的自定制

--megafunction wizard: %Altera SOPC Builder%
--GENERATION: STANDARD
--VERSION: WM1.0


--Legal Notice: (C)2005 Altera Corporation. All rights reserved.  Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors.  Please refer to the applicable
--agreement for further details.

library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library std;
use std.textio.all;

entity boot_rom_s1_arbitrator is 
        port (
              -- inputs:
                 signal boot_rom_s1_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal clk : IN STD_LOGIC;
                 signal cpu_data_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                 signal cpu_data_master_byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal cpu_data_master_read : IN STD_LOGIC;
                 signal cpu_data_master_waitrequest : IN STD_LOGIC;
                 signal cpu_data_master_write : IN STD_LOGIC;
                 signal cpu_data_master_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal cpu_instruction_master_address_to_slave : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
                 signal cpu_instruction_master_latency_counter : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
                 signal cpu_instruction_master_read : IN STD_LOGIC;
                 signal reset_n : IN STD_LOGIC;

              -- outputs:
                 signal boot_rom_s1_address : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
                 signal boot_rom_s1_byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
                 signal boot_rom_s1_chipselect : OUT STD_LOGIC;
                 signal boot_rom_s1_clken : OUT STD_LOGIC;
                 signal boot_rom_s1_readdata_from_sa : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal boot_rom_s1_write : OUT STD_LOGIC;
                 signal boot_rom_s1_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                 signal cpu_data_master_granted_boot_rom_s1 : OUT STD_LOGIC;
                 signal cpu_data_master_qualified_request_boot_rom_s1 : OUT STD_LOGIC;
                 signal cpu_data_master_read_data_valid_boot_rom_s1 : OUT STD_LOGIC;
                 signal cpu_data_master_requests_boot_rom_s1 : OUT STD_LOGIC;
                 signal cpu_instruction_master_granted_boot_rom_s1 : OUT STD_LOGIC;
                 signal cpu_instruction_master_qualified_request_boot_rom_s1 : OUT STD_LOGIC;
                 signal cpu_instruction_master_read_data_valid_boot_rom_s1 : OUT STD_LOGIC;
                 signal cpu_instruction_master_requests_boot_rom_s1 : OUT STD_LOGIC;
                 signal d1_boot_rom_s1_end_xfer : OUT STD_LOGIC;
                 signal registered_cpu_data_master_read_data_valid_boot_rom_s1 : OUT STD_LOGIC
              );
attribute auto_dissolve : boolean;
attribute auto_dissolve of boot_rom_s1_arbitrator : entity is FALSE;
end entity boot_rom_s1_arbitrator;


architecture europa of boot_rom_s1_arbitrator is
                signal boot_rom_s1_allgrants :  STD_LOGIC;
                signal boot_rom_s1_allow_new_arb_cycle :  STD_LOGIC;
                signal boot_rom_s1_any_continuerequest :  STD_LOGIC;
                signal boot_rom_s1_arb_addend :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal boot_rom_s1_arb_counter_enable :  STD_LOGIC;
                signal boot_rom_s1_arb_share_counter :  STD_LOGIC_VECTOR (2 DOWNTO 0);
                signal boot_rom_s1_arb_share_counter_next_value :  STD_LOGIC_VECTOR (2 DOWNTO 0);
                signal boot_rom_s1_arb_share_set_values :  STD_LOGIC_VECTOR (2 DOWNTO 0);
                signal boot_rom_s1_arb_winner :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal boot_rom_s1_arbitration_holdoff_internal :  STD_LOGIC;
                signal boot_rom_s1_beginbursttransfer_internal :  STD_LOGIC;
                signal boot_rom_s1_begins_xfer :  STD_LOGIC;
                signal boot_rom_s1_chosen_master_double_vector :  STD_LOGIC_VECTOR (3 DOWNTO 0);
                signal boot_rom_s1_chosen_master_rot_left :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal boot_rom_s1_end_xfer :  STD_LOGIC;
                signal boot_rom_s1_firsttransfer :  STD_LOGIC;
                signal boot_rom_s1_grant_vector :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal boot_rom_s1_in_a_read_cycle :  STD_LOGIC;
                signal boot_rom_s1_in_a_write_cycle :  STD_LOGIC;
                signal boot_rom_s1_master_qreq_vector :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal boot_rom_s1_saved_chosen_master_vector :  STD_LOGIC_VECTOR (1 DOWNTO 0);
                signal boot_rom_s1_slavearbiterlockenable :  STD_LOGIC;
                signal boot_rom_s1_waits_for_read :  STD_LOGIC;
                signal boot_rom_s1_waits_for_write :  STD_LOGIC;
                signal cpu_data_master_arbiterlock :  STD_LOGIC;
                signal cpu_data_master_continuerequest :  STD_LOGIC;
                signal cpu_data_master_read_data_valid_boot_rom_s1_shift_register :  STD_LOGIC;
                signal cpu_data_master_read_data_valid_boot_rom_s1_shift_register_in :  STD_LOGIC;
                signal cpu_data_master_saved_grant_boot_rom_s1 :  STD_LOGIC;
                signal cpu_instruction_master_arbiterlock :  STD_LOGIC;
                signal cpu_instruction_master_continuerequest :  STD_LOGIC;
                signal cpu_instruction_master_read_data_valid_boot_rom_s1_shift_register :  STD_LOGIC;
                signal cpu_instruction_master_read_data_valid_boot_rom_s1_shift_register_in :  STD_LOGIC;
                signal cpu_instruction_master_saved_grant_boot_rom_s1 :  STD_LOGIC;
                signal d1_reasons_to_wait :  STD_LOGIC;
                signal in_a_read_cycle :  STD_LOGIC;
                signal in_a_write_cycle :  STD_LOGIC;
                signal internal_cpu_data_master_granted_boot_rom_s1 :  STD_LOGIC;
                signal internal_cpu_data_master_qualified_request_boot_rom_s1 :  STD_LOGIC;
                signal internal_cpu_data_master_requests_boot_rom_s1 :  STD_LOGIC;
                signal internal_cpu_instruction_master_granted_boot_rom_s1 :  STD_LOGIC;
                signal internal_cpu_instruction_master_qualified_request_boot_rom_s1 :  STD_LOGIC;
                signal internal_cpu_instruction_master_requests_boot_rom_s1 :  STD_LOGIC;
                signal last_cycle_cpu_data_master_granted_slave_boot_rom_s1 :  STD_LOGIC;
                signal last_cycle_cpu_instruction_master_granted_slave_boot_rom_s1 :  STD_LOGIC;
                signal p1_cpu_data_master_read_data_valid_boot_rom_s1_shift_register :  STD_LOGIC;
                signal p1_cpu_instruction_master_read_data_valid_boot_rom_s1_shift_register :  STD_LOGIC;
                signal wait_for_boot_rom_s1_counter :  STD_LOGIC;

begin

  process (clk, reset_n)
  begin
    if reset_n = '0' then
      d1_reasons_to_wait <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if (std_logic_vector'("00000000000000000000000000000001")) /= std_logic_vector'("00000000000000000000000000000000") then 
        d1_reasons_to_wait <= NOT boot_rom_s1_end_xfer;
      end if;
    end if;

  end process;

  boot_rom_s1_begins_xfer <= NOT d1_reasons_to_wait AND ((internal_cpu_data_master_qualified_request_boot_rom_s1 OR internal_cpu_instruction_master_qualified_request_boot_rom_s1));
  --assign boot_rom_s1_readdata_from_sa = boot_rom_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  boot_rom_s1_readdata_from_sa <= boot_rom_s1_readdata;
  internal_cpu_data_master_requests_boot_rom_s1 <= to_std_logic(((Std_Logic_Vector'(cpu_data_master_address_to_slave(23 DOWNTO 11) & std_logic_vector'("00000000000")) = std_logic_vector'("101000000000100000000000")))) AND ((cpu_data_master_read OR cpu_data_master_write));
  --registered rdv signal_name registered_cpu_data_master_read_data_valid_boot_rom_s1 assignment, which is an e_assign
  registered_cpu_data_master_read_data_valid_boot_rom_s1 <= cpu_data_master_read_data_valid_boot_rom_s1_shift_register_in;
  --boot_rom_s1_arb_share_counter set values, which is an e_mux
  boot_rom_s1_arb_share_set_values <= std_logic_vector'("001");
  --boot_rom_s1_arb_share_counter_next_value assignment, which is an e_assign
  boot_rom_s1_arb_share_counter_next_value <= A_EXT (A_WE_StdLogicVector((std_logic'(boot_rom_s1_firsttransfer) = '1'), (((std_logic_vector'("000000000000000000000000000000") & (boot_rom_s1_arb_share_set_values)) - std_logic_vector'("000000000000000000000000000000001"))), A_WE_StdLogicVector((std_logic'(or_reduce(boot_rom_s1_arb_share_counter)) = '1'), (((std_logic_vector'("000000000000000000000000000000") & (boot_rom_s1_arb_share_counter)) - std_logic_vector'("000000000000000000000000000000001"))), std_logic_vector'("000000000000000000000000000000000"))), 3);
  --boot_rom_s1_allgrants all slave grants, which is an e_mux
  boot_rom_s1_allgrants <= ((or_reduce(boot_rom_s1_grant_vector) OR or_reduce(boot_rom_s1_grant_vector)) OR or_reduce(boot_rom_s1_grant_vector)) OR or_reduce(boot_rom_s1_grant_vector);
  --boot_rom_s1_end_xfer assignment, which is an e_assign
  boot_rom_s1_end_xfer <= NOT ((boot_rom_s1_waits_for_read OR boot_rom_s1_waits_for_write));
  --boot_rom_s1_arb_share_counter arbitration counter enable, which is an e_assign
  boot_rom_s1_arb_counter_enable <= boot_rom_s1_end_xfer AND boot_rom_s1_allgrants;
  --boot_rom_s1_arb_share_counter counter, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      boot_rom_s1_arb_share_counter <= std_logic_vector'("000");
    elsif clk'event and clk = '1' then
      if std_logic'(boot_rom_s1_arb_counter_enable) = '1' then 
        boot_rom_s1_arb_share_counter <= boot_rom_s1_arb_share_counter_next_value;
      end if;
    end if;

  end process;

  --boot_rom_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  process (clk, reset_n)
  begin
    if reset_n = '0' then
      boot_rom_s1_slavearbiterlockenable <= std_logic'('0');
    elsif clk'event and clk = '1' then
      if std_logic'((or_reduce(boot_rom_s1_master_qreq_vector) AND boot_rom_s1_end_xfer)) = '1' then 
        boot_rom_s1_slavearbiterlockenable <= or_reduce(boot_rom_s1_arb_share_counter_next_value);
      end if;
    end if;

  end process;

  --cpu/data_master boot_rom/s1 arbiterlock, which is an e_assign
  cpu_data_master_arbiterlock <= boot_rom_s1_slavearbiterlockenable AND cpu_data_master_continuerequest;
  --cpu/instruction_master boot_rom/s1 arbiterlock, which is an e_assign
  cpu_instruction_master_arbiterlock <= boot_rom_s1_slavearbiterlockenable AND cpu_instruction_master_continuerequest;
  --cpu/instruction_master granted boot_rom/s1 last time, which is an e_register
  process (clk, reset_n)