📄 sc-dsc.fit.rpt
字号:
Fitter report for SC-DSC compilation.
Fri Jun 01 14:01:32 2007
Version 3.0 Build 199 06/26/2003 SJ Full Version
Command: quartus_fit --import_settings_files=off --export_settings_files=off sc-dsc -c SC-DSC
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; Table of Contents ;
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1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Elapsed Time
5. Fitter Summary
6. Fitter Settings
7. Fitter Device Options
8. Fitter Equations
9. Floorplan View
10. Pin-Out File
11. Resource Usage Summary
12. Input Pins
13. Output Pins
14. All Package Pins
15. I/O Standard
16. Dedicated Inputs I/O
17. Output Pin Load For Reported TCO
18. Fitter Resource Utilization by Entity
19. Control Signals
20. Global & Other Fast Signals
21. Non-Global High Fan-Out Signals
22. Interconnect Usage Summary
23. LAB External Interconnect
24. LAB Macrocells
25. Logic Cell Interconnection
26. Fitter Messages
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; Legal Notice ;
----------------
Copyright (C) 1991-2003 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
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; Flow Summary ;
-----------------------------------------------------------------
; Flow Status ; Successful - Fri Jun 01 14:01:32 2007 ;
; Compiler Setting Name ; SC-DSC ;
; Top-level Entity Name ; SC-DSC ;
; Family ; MAX7000S ;
; Device ; EPM7128SLC84-15 ;
; Total macrocells ; 17 / 128 ( 13 % ) ;
; Total pins ; 8 / 68 ( 11 % ) ;
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-----------------------------------------------
; Flow Settings ;
-----------------------------------------------
; Option ; Setting ;
-----------------------------------------------
; Start date & time ; 06/01/2007 14:01:29 ;
; Main task ; Compilation ;
; Compiler Setting Name ; SC-DSC ;
-----------------------------------------------
---------------------------------------
; Flow Elapsed Time ;
---------------------------------------
; Module Name ; Elapsed Time ;
---------------------------------------
; Analysis & Synthesis ; 00:00:01 ;
; Fitter ; 00:00:00 ;
; Total ; 00:00:01 ;
---------------------------------------
-----------------------------------------------------------------
; Fitter Summary ;
-----------------------------------------------------------------
; Fitter Status ; Successful - Fri Jun 01 14:01:32 2007 ;
; Compiler Setting Name ; SC-DSC ;
; Top-level Entity Name ; SC-DSC ;
; Family ; MAX7000S ;
; Device ; EPM7128SLC84-15 ;
; Total macrocells ; 17 / 128 ( 13 % ) ;
; Total pins ; 8 / 68 ( 11 % ) ;
-----------------------------------------------------------------
-------------------------------------------------------------------
; Fitter Settings ;
-------------------------------------------------------------------
; Option ; Setting ;
-------------------------------------------------------------------
; Device ; EPM7128SLC84-15 ;
; Fast Fit compilation ; Off ;
; Optimize IOC register placement for timing ; On ;
; Optimize timing ; Normal Compilation ;
-------------------------------------------------------------------
---------------------------------------------------------------------------
; Fitter Device Options ;
---------------------------------------------------------------------------
; Option ; Setting ;
---------------------------------------------------------------------------
; Auto-restart configuration after error ; Off ;
; Release clears before tri-states ; Off ;
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Reserve all unused pins ; As output driving ground ;
; Security bit ; Off ;
; Base pin-out file on sameframe device ; Off ;
---------------------------------------------------------------------------
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; Fitter Equations ;
---------------------
The equations can be found in E:\3 实验 扰码与解扰（用Quartus II)\SC\SC-DSC.fit.eqn.
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; Floorplan View ;
-------------------
Floorplan report data cannot be output to ASCII.
Please use Quartus II to view the floorplan report data.
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; Pin-Out File ;
-----------------
The pin-out file can be found in E:\3 实验 扰码与解扰（用Quartus II)\SC\SC-DSC.pin.
----------------------------------------------------
; Resource Usage Summary ;
----------------------------------------------------
; Resource ; Usage ;
----------------------------------------------------
; Logic cells ; 17 / 128 ( 13 % ) ;
; Registers ; 17 / 128 ( 13 % ) ;
; Number of pterms used ; 24 ;
; User inserted logic cells ; 0 ;
; I/O pins ; 8 / 68 ( 11 % ) ;
; -- Clock pins ; 1 / 2 ( 50 % ) ;
; -- Dedicated input pins ; 0 / 2 ( 0 % ) ;
; Global signals ; 1 ;
; Shareable expanders ; 0 / 128 ( 0 % ) ;
; Parallel expanders ; 0 / 120 ( 0 % ) ;
; Cells using turbo bit ; 17 / 128 ( 13 % ) ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 17 ;
; Total fan-out ; 44 ;
; Average fan-out ; 1.76 ;
----------------------------------------------------
----------------------------------------------------------------------------------------------------------------------------------------------
; Input Pins ;
----------------------------------------------------------------------------------------------------------------------------------------------
; Name ; Pin # ; I/O Bank ; LAB ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; I/O Standard ; Location assigned by ;
----------------------------------------------------------------------------------------------------------------------------------------------
; clk ; 83 ; -- ; -- ; 17 ; 0 ; yes ; no ; TTL ; User ;
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; Output Pins ;
-------------------------------------------------------------------------------------------------------------------------------------
; Name ; Pin # ; I/O Bank ; LAB ; Output Register ; Slow Slew Rate ; Open Drain ; Turbo Bit ; I/O Standard ; Location assigned by ;
-------------------------------------------------------------------------------------------------------------------------------------
; dscout ; 40 ; -- ; D ; no ; no ; no ; yes ; TTL ; User ;
; nrz ; 37 ; -- ; D ; no ; no ; no ; yes ; TTL ; User ;
; scout ; 39 ; -- ; D ; no ; no ; no ; yes ; TTL ; User ;
-------------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------
; All Package Pins ;
-----------------------------------------------------------------
; Location ; I/O Bank ; Pin Name/Usage ; I/O Standard ; Voltage ;
-----------------------------------------------------------------
; 1 ; -- ; GND+ ; ; ;
; 2 ; -- ; GND+ ; ; ;
; 3 ; -- ; VCCINT ; ; 5.0V ;
; 4 ; -- ; GND* ; ; ;
; 5 ; -- ; GND* ; ; ;
; 6 ; -- ; GND* ; ; ;
; 7 ; -- ; GND ; ; ;
; 8 ; -- ; GND* ; ; ;
; 9 ; -- ; GND* ; ; ;
; 10 ; -- ; GND* ; ; ;
; 11 ; -- ; GND* ; ; ;
; 12 ; -- ; GND* ; ; ;
; 13 ; -- ; VCCIO ; ; 5.0V ;
; 14 ; -- ; +TDI ; TTL ; ;
; 15 ; -- ; GND* ; ; ;
; 16 ; -- ; GND* ; ; ;
; 17 ; -- ; GND* ; ; ;
; 18 ; -- ; GND* ; ; ;
; 19 ; -- ; GND ; ; ;
; 20 ; -- ; GND* ; ; ;
; 21 ; -- ; GND* ; ; ;
; 22 ; -- ; GND* ; ; ;
; 23 ; -- ; +TMS ; TTL ; ;
; 24 ; -- ; GND* ; ; ;
; 25 ; -- ; GND* ; ; ;
; 26 ; -- ; VCCIO ; ; 5.0V ;
; 27 ; -- ; GND* ; ; ;
; 28 ; -- ; GND* ; ; ;
; 29 ; -- ; GND* ; ; ;
; 30 ; -- ; GND* ; ; ;
; 31 ; -- ; GND* ; ; ;
; 32 ; -- ; GND ; ; ;
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