tcdg.vhdl.txt

直接仿真就可以使用

end simple;






--------------------------------------------------------------------------
---------------------------------------------------- TCDG   --------------
--------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
entity tcdg is
    port (
        key   : in  std_logic_vector(63 downto 0);
        d     : in  std_logic_vector(63 downto 0);
        start : in  std_logic;
        crypt : in  std_logic;
        clk   : in  std_logic;
        nreset: in  std_logic;
        q     : out std_logic_vector(63 downto 0);
        done  : out std_logic
    );
end;


-------------------- Architecture tcdg --------------------------------

library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

architecture simple of TCDG is

    component subkey 
    port (
         key    : in  std_logic_vector(63 downto 0);
         sel    : in  std_logic_vector(3 downto 0);
         subkey : out std_logic_vector(47 downto 0)
    );
    end component;



    component subs_1 
    port (
         entree : in  std_logic_vector(5 downto 0);
         sortie : out std_logic_vector(3 downto 0)
    );
    end component;


    signal s_out_1 : std_logic_vector(3 downto 0);
    signal s_in_1  : std_logic_vector(5 downto 0);

    component subs_2 
    port (
         entree : in  std_logic_vector(5 downto 0);
         sortie : out std_logic_vector(3 downto 0)
    );
    end component;


    signal s_out_2 : std_logic_vector(3 downto 0);
    signal s_in_2  : std_logic_vector(5 downto 0);

    component subs_3 
    port (
         entree : in  std_logic_vector(5 downto 0);
         sortie : out std_logic_vector(3 downto 0)
    );
    end component;


    signal s_out_3 : std_logic_vector(3 downto 0);
    signal s_in_3  : std_logic_vector(5 downto 0);

    component subs_4 
    port (
         entree : in  std_logic_vector(5 downto 0);
         sortie : out std_logic_vector(3 downto 0)
    );
    end component;


    signal s_out_4 : std_logic_vector(3 downto 0);
    signal s_in_4  : std_logic_vector(5 downto 0);

    component subs_5 
    port (
         entree : in  std_logic_vector(5 downto 0);
         sortie : out std_logic_vector(3 downto 0)
    );
    end component;


    signal s_out_5 : std_logic_vector(3 downto 0);
    signal s_in_5  : std_logic_vector(5 downto 0);

    component subs_6 
    port (
         entree : in  std_logic_vector(5 downto 0);
         sortie : out std_logic_vector(3 downto 0)
    );
    end component;


    signal s_out_6 : std_logic_vector(3 downto 0);
    signal s_in_6  : std_logic_vector(5 downto 0);

    component subs_7 
    port (
         entree : in  std_logic_vector(5 downto 0);
         sortie : out std_logic_vector(3 downto 0)
    );
    end component;


    signal s_out_7 : std_logic_vector(3 downto 0);
    signal s_in_7  : std_logic_vector(5 downto 0);

    component subs_8 
    port (
         entree : in  std_logic_vector(5 downto 0);
         sortie : out std_logic_vector(3 downto 0)
    );
    end component;


    signal s_out_8      : std_logic_vector(3 downto 0);
    signal s_in_8       : std_logic_vector(5 downto 0);


    signal xorkey       : std_logic_vector(47 downto 0);
    signal w            : std_logic_vector(31 downto 0);
    signal t            : std_logic_vector(31 downto 0);
    signal kkey         : std_logic_vector(47 downto 0);
    signal erkey        : std_logic_vector(47 downto 0);
    signal rkey         : std_logic_vector(31 downto 0);
    signal lkey         : std_logic_vector(31 downto 0);
    signal r0           : std_logic_vector(31 downto 0);
    signal l0           : std_logic_vector(31 downto 0);
    signal state        : std_logic_vector( 3 downto 0);
    signal next_state   : std_logic_vector( 3 downto 0);
    signal rkeyreg      : std_logic_vector(31 downto 0);
    signal next_rkeyreg : std_logic_vector(31 downto 0);
    signal pnewbkey     : std_logic_vector(31 downto 0);
    signal rkey_in      : std_logic_vector(31 downto 0);
    signal lkeyreg      : std_logic_vector(31 downto 0);
    signal next_lkeyreg : std_logic_vector(31 downto 0);
    signal k            : std_logic_vector(63 downto 0);
    signal datainreg    : std_logic_vector(63 downto 0);
    signal id           : std_logic_vector(63 downto 0);
    signal keysel       : std_logic_vector(3 downto 0);
    signal start_prev   : std_logic;
    signal ff_crypt     : std_logic;
    signal next_ff_crypt: std_logic;

begin


    P14 : process(state,ff_crypt)
    begin
            if (ff_crypt='1') then 
            keysel <= state;
        else
            keysel <= not state;
        end if;
    end process;


    i_subkey : subkey
    port map (key => key, sel => keysel,subkey => kkey );


    id <= datainreg;


    l0<=id(6)&id(14)&id(22)&id(30)&id(38)&id(46)&id(54)&id(62)&id(4)&id(12)&id(20)&id(28)&id(36)&id(44)&id(52)&id(60)&id(2)&id(10)&id(18)&id(26)&id(34)&id(42)&id(50)&id(58)&id(0)&id(8)&id(16)&id(24)&id(32)&id(40)&id(48)&id(56);
    r0<=id(7)&id(15)&id(23)&id(31)&id(39)&id(47)&id(55)&id(63)&id(5)&id(13)&id(21)&id(29)&id(37)&id(45)&id(53)&id(61)&id(3)&id(11)&id(19)&id(27)&id(35)&id(43)&id(51)&id(59)&id(1)&id(9)&id(17)&id(25)&id(33)&id(41)&id(49)&id(57);


    P17 : process(state,r0,rkeyreg,l0,lkeyreg)
    begin
        if (state="0000") then 
            rkey_in <= r0;
            lkey    <= l0;
        else
            rkey_in <= rkeyreg;
            lkey    <= lkeyreg;
        end if;
    end process;


    t <= rkey_in;


    erkey<=t(0)&t(31 downto 27)&t(28 downto 23)&t(24 downto 19)&t(20 downto 15)&t(16 downto 11)&t(12 downto 7)&t(8 downto 3)&t(4 downto 0)&t(31);

    xorkey <= erkey xor kkey;
    s_in_1 <= xorkey(47 downto 42);
    s_in_2 <= xorkey(41 downto 36);
    s_in_3 <= xorkey(35 downto 30);
    s_in_4 <= xorkey(29 downto 24);
    s_in_5 <= xorkey(23 downto 18);
    s_in_6 <= xorkey(17 downto 12);
    s_in_7 <= xorkey(11 downto  6);
    s_in_8 <= xorkey( 5 downto  0);
    
    i_subs_1 : subs_1
    port map (entree => s_in_1,sortie => s_out_1);

    i_subs_2 : subs_2
    port map (entree => s_in_2,sortie => s_out_2);

    i_subs_3 : subs_3
    port map (entree => s_in_3,sortie => s_out_3);

    i_subs_4 : subs_4
    port map (entree => s_in_4,sortie => s_out_4);

    i_subs_5 : subs_5
    port map (entree => s_in_5,sortie => s_out_5);

    i_subs_6 : subs_6
    port map (entree => s_in_6,sortie => s_out_6);

    i_subs_7 : subs_7
    port map (entree => s_in_7,sortie => s_out_7);

    i_subs_8 : subs_8
    port map (entree => s_in_8,sortie => s_out_8);


    w<=s_out_1&s_out_2&s_out_3&s_out_4&s_out_5&s_out_6&s_out_7&s_out_8;

    pnewbkey<=w(16)&w(25)&w(12)&w(11)&w(3)&w(20)&w(4)&w(15)&w(31)&w(17)&w(9)&w(6)&w(27)&w(14)&w(1)&w(22)&w(30)&w(24)&w(8)&w(18)&w(0)&w(5)&w(29)&w(23)&w(13)&w(19)&w(2)&w(26)&w(10)&w(21)&w(28)&w(7);


    rkey <= pnewbkey xor lkey;
    k    <= rkey & rkeyreg;

    q<=k(24)&k(56)&k(16)&k(48)&k(8)&k(40)&k(0)&k(32)&k(25)&k(57)&k(17)&k(49)&k(9)&k(41)&k(1)&k(33)&k(26)&k(58)&k(18)&k(50)&k(10)&k(42)&k(2)&k(34)&k(27)&k(59)&k(19)&k(51)&k(11)&k(43)&k(3)&k(35)&k(28)&k(60)&k(20)&k(52)&k(12)&k(44)&k(4)&k(36)&k(29)&k(61)&k(21)&k(53)&k(13)&k(45)&k(5)&k(37)&k(30)&k(62)&k(22)&k(54)&k(14)&k(46)&k(6)&k(38)&k(31)&k(63)&k(23)&k(55)&k(15)&k(47)&k(7)&k(39);


    P27 : process(start,start_prev,state)
    begin
        if ((start='1') AND (start_prev='0')) then 
            next_state <= "0000";
        else
            if (state="1111") then 
                next_state <= "1111";
            else
                next_state <= state + "1";
            end if;
        end if;
    end process;


    P27_2 : process(start,crypt,ff_crypt,start_prev)
    begin
        if ((start='1') AND (start_prev='0')) then 
            next_ff_crypt <= crypt;
        else
            next_ff_crypt <= ff_crypt;
        end if;
    end process;


    P28 : process(rkeyreg,lkeyreg,state,rkey,rkey_in)
    begin
        if (state="1111") then 
            next_rkeyreg <= rkeyreg;
            next_lkeyreg <= lkeyreg;
            done <= '1';
        else
            next_rkeyreg <= rkey;
            next_lkeyreg <= rkey_in;
            done <= '0';
        end if;
    end process;

    ------------------------------------------------------------- 
        ---------------------------  MEMORIES  ---------------------- 
        ------------------------------------------------------------- 
    P29 : process(clk, nreset)
    begin
        if (nreset='0') then
            state      <= (others => '0');
            rkeyreg    <= (others => '0');
            lkeyreg    <= (others => '0');
            start_prev <= '0';
            datainreg  <= (others => '0');
            ff_crypt   <= '0';
        else
            if (clk='1' and clk'event) then
                state      <= next_state;
                rkeyreg    <= next_rkeyreg;
                lkeyreg    <= next_lkeyreg;
                start_prev <= start;
                datainreg  <= d;
                ff_crypt   <= next_ff_crypt;
            end if;
        end if;
    end process;


end simple;