tcdg.vhdl.txt

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            when "010100" => sortie<="0010";
            when "010101" => sortie<="0001";
            when "010110" => sortie<="1101";
            when "010111" => sortie<="1010";
            when "011000" => sortie<="1100";
            when "011001" => sortie<="0110";
            when "011010" => sortie<="0000";
            when "011011" => sortie<="1001";
            when "011100" => sortie<="0101";
            when "011101" => sortie<="1011";
            when "011110" => sortie<="1010";
            when "011111" => sortie<="0101";
            when "100000" => sortie<="0000";
            when "100001" => sortie<="1101";
            when "100010" => sortie<="1110";
            when "100011" => sortie<="1000";
            when "100100" => sortie<="0111";
            when "100101" => sortie<="1010";
            when "100110" => sortie<="1011";
            when "100111" => sortie<="0001";
            when "101000" => sortie<="1010";
            when "101001" => sortie<="0011";
            when "101010" => sortie<="0100";
            when "101011" => sortie<="1111";
            when "101100" => sortie<="1101";
            when "101101" => sortie<="0100";
            when "101110" => sortie<="0001";
            when "101111" => sortie<="0010";
            when "110000" => sortie<="0101";
            when "110001" => sortie<="1011";
            when "110010" => sortie<="1000";
            when "110011" => sortie<="0110";
            when "110100" => sortie<="1100";
            when "110101" => sortie<="0111";
            when "110110" => sortie<="0110";
            when "110111" => sortie<="1100";
            when "111000" => sortie<="1001";
            when "111001" => sortie<="0000";
            when "111010" => sortie<="0011";
            when "111011" => sortie<="0101";
            when "111100" => sortie<="0010";
            when "111101" => sortie<="1110";
            when "111110" => sortie<="1111";
            when others   => sortie<="1001";
        end case;
    end process;


end simple;




--------------------------------------------------------------------------
------------------------------------------------------ SUBS_3 ------------
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity subs_3 is
    port (
        entree : in  std_logic_vector(5 downto 0);
        sortie : out std_logic_vector(3 downto 0)
    );
end;


---------- Architecture subs_3 ---------- 
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

architecture simple of subs_3 is
begin
    P8 : process(entree)
    begin
        case entree is
            when "000000" => sortie<="1010";
            when "000001" => sortie<="1101";
            when "000010" => sortie<="0000";
            when "000011" => sortie<="0111";
            when "000100" => sortie<="1001";
            when "000101" => sortie<="0000";
            when "000110" => sortie<="1110";
            when "000111" => sortie<="1001";
            when "001000" => sortie<="0110";
            when "001001" => sortie<="0011";
            when "001010" => sortie<="0011";
            when "001011" => sortie<="0100";
            when "001100" => sortie<="1111";
            when "001101" => sortie<="0110";
            when "001110" => sortie<="0101";
            when "001111" => sortie<="1010";
            when "010000" => sortie<="0001";
            when "010001" => sortie<="0010";
            when "010010" => sortie<="1101";
            when "010011" => sortie<="1000";
            when "010100" => sortie<="1100";
            when "010101" => sortie<="0101";
            when "010110" => sortie<="0111";
            when "010111" => sortie<="1110";
            when "011000" => sortie<="1011";
            when "011001" => sortie<="1100";
            when "011010" => sortie<="0100";
            when "011011" => sortie<="1011";
            when "011100" => sortie<="0010";
            when "011101" => sortie<="1111";
            when "011110" => sortie<="1000";
            when "011111" => sortie<="0001";
            when "100000" => sortie<="1101";
            when "100001" => sortie<="0001";
            when "100010" => sortie<="0110";
            when "100011" => sortie<="1010";
            when "100100" => sortie<="0100";
            when "100101" => sortie<="1101";
            when "100110" => sortie<="1001";
            when "100111" => sortie<="0000";
            when "101000" => sortie<="1000";
            when "101001" => sortie<="0110";
            when "101010" => sortie<="1111";
            when "101011" => sortie<="1001";
            when "101100" => sortie<="0011";
            when "101101" => sortie<="1000";
            when "101110" => sortie<="0000";
            when "101111" => sortie<="0111";
            when "110000" => sortie<="1011";
            when "110001" => sortie<="0100";
            when "110010" => sortie<="0001";
            when "110011" => sortie<="1111";
            when "110100" => sortie<="0010";
            when "110101" => sortie<="1110";
            when "110110" => sortie<="1100";
            when "110111" => sortie<="0011";
            when "111000" => sortie<="0101";
            when "111001" => sortie<="1011";
            when "111010" => sortie<="1010";
            when "111011" => sortie<="0101";
            when "111100" => sortie<="1110";
            when "111101" => sortie<="0010";
            when "111110" => sortie<="0111";
            when others   => sortie<="1100";
        end case;
    end process;


end simple;




--------------------------------------------------------------------------
------------------------------------------------------ SUBS_4 ------------
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity subs_4 is
    port (
        entree : in  std_logic_vector(5 downto 0);
        sortie : out std_logic_vector(3 downto 0)
    );
end;


---------- Architecture subs_4 ---------- 
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

architecture simple of subs_4 is
begin
    P9 : process(entree)
    begin
        case entree is
            when "000000" => sortie<="0111";
            when "000001" => sortie<="1101";
            when "000010" => sortie<="1101";
            when "000011" => sortie<="1000";
            when "000100" => sortie<="1110";
            when "000101" => sortie<="1011";
            when "000110" => sortie<="0011";
            when "000111" => sortie<="0101";
            when "001000" => sortie<="0000";
            when "001001" => sortie<="0110";
            when "001010" => sortie<="0110";
            when "001011" => sortie<="1111";
            when "001100" => sortie<="1001";
            when "001101" => sortie<="0000";
            when "001110" => sortie<="1010";
            when "001111" => sortie<="0011";
            when "010000" => sortie<="0001";
            when "010001" => sortie<="0100";
            when "010010" => sortie<="0010";
            when "010011" => sortie<="0111";
            when "010100" => sortie<="1000";
            when "010101" => sortie<="0010";
            when "010110" => sortie<="0101";
            when "010111" => sortie<="1100";
            when "011000" => sortie<="1011";
            when "011001" => sortie<="0001";
            when "011010" => sortie<="1100";
            when "011011" => sortie<="1010";
            when "011100" => sortie<="0100";
            when "011101" => sortie<="1110";
            when "011110" => sortie<="1111";
            when "011111" => sortie<="1001";
            when "100000" => sortie<="1010";
            when "100001" => sortie<="0011";
            when "100010" => sortie<="0110";
            when "100011" => sortie<="1111";
            when "100100" => sortie<="1001";
            when "100101" => sortie<="0000";
            when "100110" => sortie<="0000";
            when "100111" => sortie<="0110";
            when "101000" => sortie<="1100";
            when "101001" => sortie<="1010";
            when "101010" => sortie<="1011";
            when "101011" => sortie<="0001";
            when "101100" => sortie<="0111";
            when "101101" => sortie<="1101";
            when "101110" => sortie<="1101";
            when "101111" => sortie<="1000";
            when "110000" => sortie<="1111";
            when "110001" => sortie<="1001";
            when "110010" => sortie<="0001";
            when "110011" => sortie<="0100";
            when "110100" => sortie<="0011";
            when "110101" => sortie<="0101";
            when "110110" => sortie<="1110";
            when "110111" => sortie<="1011";
            when "111000" => sortie<="0101";
            when "111001" => sortie<="1100";
            when "111010" => sortie<="0010";
            when "111011" => sortie<="0111";
            when "111100" => sortie<="1000";
            when "111101" => sortie<="0010";
            when "111110" => sortie<="0100";
            when others   => sortie<="1110";
        end case;
    end process;


end simple;




--------------------------------------------------------------------------
------------------------------------------------------ SUBS_5 ------------
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity subs_5 is
    port (
        entree : in  std_logic_vector(5 downto 0);
        sortie : out std_logic_vector(3 downto 0)
    );
end;


---------- Architecture subs_5 ---------- 
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

architecture simple of subs_5 is
begin
    P10 : process(entree)
    begin
        case entree is
            when "000000" => sortie<="0010";
            when "000001" => sortie<="1110";
            when "000010" => sortie<="1100";
            when "000011" => sortie<="1011";
            when "000100" => sortie<="0100";
            when "000101" => sortie<="0010";
            when "000110" => sortie<="0001";
            when "000111" => sortie<="1100";
            when "001000" => sortie<="0111";
            when "001001" => sortie<="0100";
            when "001010" => sortie<="1010";
            when "001011" => sortie<="0111";
            when "001100" => sortie<="1011";
            when "001101" => sortie<="1101";
            when "001110" => sortie<="0110";
            when "001111" => sortie<="0001";
            when "010000" => sortie<="1000";
            when "010001" => sortie<="0101";
            when "010010" => sortie<="0101";
            when "010011" => sortie<="0000";
            when "010100" => sortie<="0011";
            when "010101" => sortie<="1111";
            when "010110" => sortie<="1111";
            when "010111" => sortie<="1010";
            when "011000" => sortie<="1101";
            when "011001" => sortie<="0011";
            when "011010" => sortie<="0000";
            when "011011" => sortie<="1001";
            when "011100" => sortie<="1110";
            when "011101" => sortie<="1000";
            when "011110" => sortie<="1001";
            when "011111" => sortie<="0110";
            when "100000" => sortie<="0100";
            when "100001" => sortie<="1011";
            when "100010" => sortie<="0010";
            when "100011" => sortie<="1000";
            when "100100" => sortie<="0001";
            when "100101" => sortie<="1100";
            when "100110" => sortie<="1011";
            when "100111" => sortie<="0111";
            when "101000" => sortie<="1010";
            when "101001" => sortie<="0001";
            when "101010" => sortie<="1101";
            when "101011" => sortie<="1110";