ram.v

来自「精简CPU设计」· Verilog 代码 · 共 21 行

module ram(data,addr,ena,read,write);
 inout[7:0] data;
 input[9:0] addr;
 input ena;
 input read,write;
 reg[7:0] mem[0:1023];
 
 assign data=(read&&ena)?mem[addr]:8'bz;
 
/* always @(read or ena or addr)
    if(read&&ena)
      data<=mem[addr];
    else
      data<=8'hzz;  */
   
 always @(posedge write)
  begin
   mem[addr]<=data;
  end
endmodule