machinect1.v.bak

来自「精简CPU设计」· BAK 代码 · 共 15 行

module machinect1(ena,fetch,rst);
    output ena;
    input fetch,rst;
    reg ena;
    
    always @(posedge fetch or posedge rst)
       begin
           if(!rst)
              ena<=0;
           else
              ena<=1;
       end
     endmodule