accum.v

来自「精简CPU设计」· Verilog 代码 · 共 15 行

module accum(accum,data,ena,clk1,rst);
    output[7:0] accum;
    input[7:0] data;
    input ena,clk1,rst;
    reg[7:0] accum;
    
    always @(clk1)
     begin
         if(!rst)
           accum<=8'h00;
        else
           if(ena)
             accum<=data;
    end
endmodule