alu.v.bak

精简CPU设计

module alu(alu_out,zero,data,accum,alu_clk,opcode);
   output[7:0] aluout;
   output zero;
   input[2:0] opcode;
   input[7:0] data,accum;
   input alu_clk;
   reg[7:0] aluout;
   
   parameter  HLT=3'b000,
              SKZ=3'b001,
              ADD=3'b010,
              AND=3'b011,
              XOR=3'b100,
              LDA=3'b101,
              STO=3'b110,
              JMP=3'b111;
              
    assign zero=!accum;
    
    always @(posedge alu_clk)
      begin
          case(opcode)
              HLT: alu_out<=accum;
              SKZ: alu_out<=accum;
              ADD: alu_out<=data+accum;
              AND: alu_out<=data&accum;
              XOR: alu_out<=data^accum;
              LDA: alu_out<=data;
              STO: alu_out<=accum;
              JMP: alu_out<=accum;
              default: alu_out<=8'hxx;
          endcase
      end
  endmodule