_primary.vhd

来自「精简CPU设计」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity addr_decode is
    port(
        addr            : in     vl_logic_vector(12 downto 0);
        rom_sel         : out    vl_logic;
        ram_sel         : out    vl_logic
    );
end addr_decode;