riscmcu.cr.mti

精简CPU设计

E:/feng/verilog/riscmcu/machine.v {1 {vlog -work work E:/feng/verilog/riscmcu/machine.v
Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
-- Compiling module machine

Top level modules:
	machine

} {} {}} E:/feng/verilog/riscmcu/riscmcu.v {1 {vlog -work work E:/feng/verilog/riscmcu/riscmcu.v
Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
-- Compiling module register
-- Compiling module accum
-- Compiling module alu
-- Compiling module datact1
-- Compiling module adr
-- Compiling module counter
-- Compiling module machinect1
-- Compiling module machine
-- Compiling module addr_decode
-- Compiling module ram
-- Compiling module rom
-- Compiling module clk_gen
-- Compiling module riscmcu

Top level modules:
	riscmcu

} {} {}} E:/feng/verilog/riscmcu/counter.v {1 {vlog -work work E:/feng/verilog/riscmcu/counter.v
Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
-- Compiling module counter

Top level modules:
	counter

} {} {}} E:/feng/verilog/riscmcu/alu.v {1 {vlog -work work E:/feng/verilog/riscmcu/alu.v
Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
-- Compiling module alu

Top level modules:
	alu

} {} {}} E:/feng/verilog/riscmcu/datact1.v {1 {vlog -work work E:/feng/verilog/riscmcu/datact1.v
Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
-- Compiling module datact1

Top level modules:
	datact1

} {} {}} E:/feng/verilog/riscmcu/clk_gen.v {1 {vlog -work work E:/feng/verilog/riscmcu/clk_gen.v
Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
-- Compiling module clk_gen

Top level modules:
	clk_gen

} {} {}} E:/feng/verilog/riscmcu/machinect1.v {1 {vlog -work work E:/feng/verilog/riscmcu/machinect1.v
Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
-- Compiling module machinect1

Top level modules:
	machinect1

} {} {}} E:/feng/verilog/riscmcu/register.v {1 {vlog -work work E:/feng/verilog/riscmcu/register.v
Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
-- Compiling module register

Top level modules:
	register

} {} {}} E:/feng/verilog/riscmcu/addr_decode.v {1 {vlog -work work E:/feng/verilog/riscmcu/addr_decode.v
Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
-- Compiling module addr_decode

Top level modules:
	addr_decode

} {} {}} E:/feng/verilog/riscmcu/rom.v {1 {vlog -work work E:/feng/verilog/riscmcu/rom.v
Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
-- Compiling module rom

Top level modules:
	rom

} {} {}} E:/feng/verilog/riscmcu/adr.v {1 {vlog -work work E:/feng/verilog/riscmcu/adr.v
Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
-- Compiling module adr

Top level modules:
	adr

} {} {}} E:/feng/verilog/riscmcu/ram.v {1 {vlog -work work E:/feng/verilog/riscmcu/ram.v
Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
-- Compiling module ram

Top level modules:
	ram

} {} {}} E:/feng/verilog/riscmcu/accum.v {1 {vlog -work work E:/feng/verilog/riscmcu/accum.v
Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep  8 2005
-- Compiling module accum

Top level modules:
	accum

} {} {}}