display.vhd

来自「交通灯信号控制器」· VHDL 代码 · 共 61 行

--
--  File: display.vhd
--  数码管动态显示译码电路
--  输入：1KHZ时钟，两个数，
--  输出：位选col，数据led

library IEEE;
use IEEE.std_logic_1164.all;

entity display is
	port (
        reset: in STD_LOGIC;
		clk1k: in STD_LOGIC;
		col: out STD_LOGIC_VECTOR (3 downto 0);
		led: out STD_LOGIC_VECTOR (6 downto 0);
		data1: in INTEGER range 0 to 9;
		data2: in INTEGER range 0 to 9;
		data3: in INTEGER range 0 to 9;
		data4: in INTEGER range 0 to 9
	);
end display;


architecture rtl of display is
signal cnt:integer range 0 to 4;
signal data:integer range 0 to 10;
begin
	process(clk1k)
	begin
		if rising_edge(clk1k) then
			if(cnt=3) then cnt<=0;
			else cnt<=cnt+1;
			end if;
		end if;
	end process;
	
	data<=10 when reset='1' else
          data1 when cnt=1 else
	      data2 when cnt=2 else
	      data3 when cnt=3 else
		  data4;   		
	
    col<="1000" when cnt=1 else
	     "0100" when cnt=2 else
	     "0010" when cnt=3 else
		 "0001";
	
	with data select
	     led<="0110000" when 1, --1
	          "1101101" when 2, --2
	          "1111001" when 3, --3
	          "0110011" when 4, --4
	          "1011011" when 5, --5
	          "1011111" when 6, --6
	          "1110000" when 7, --7
	          "1111111" when 8, --8
	          "1111011" when 9, --9
              "1111110" when others; --0 

end rtl;