📄 counter.rpt
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FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\cpld\fenpinqi\counter.rpt
counter
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 clk
INPUT 4 key
Device-Specific Information: e:\cpld\fenpinqi\counter.rpt
counter
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 4 clr
Device-Specific Information: e:\cpld\fenpinqi\counter.rpt
counter
** EQUATIONS **
clk : INPUT;
clr : INPUT;
key : INPUT;
-- Node name is ':22' = 'bcd1n0'
-- Equation name is 'bcd1n0', location is LC6_A24, type is buried.
bcd1n0 = DFFE( _EQ001, GLOBAL(!key), GLOBAL( clr), VCC, VCC);
_EQ001 = bcd1n0 & !_LC1_A19
# !bcd1n0 & _LC1_A19;
-- Node name is ':21' = 'bcd1n1'
-- Equation name is 'bcd1n1', location is LC7_A14, type is buried.
bcd1n1 = DFFE( _EQ002, GLOBAL(!key), GLOBAL( clr), VCC, VCC);
_EQ002 = !bcd1n0 & bcd1n1 & !_LC6_A14
# bcd1n0 & !bcd1n1 & _LC1_A19 & !_LC6_A14
# bcd1n1 & !_LC1_A19;
-- Node name is ':20' = 'bcd1n2'
-- Equation name is 'bcd1n2', location is LC2_A24, type is buried.
bcd1n2 = DFFE( _EQ003, GLOBAL(!key), GLOBAL( clr), VCC, VCC);
_EQ003 = bcd1n2 & !_LC4_A24
# !bcd1n2 & _LC1_A19 & _LC4_A24
# bcd1n2 & !_LC1_A19;
-- Node name is ':19' = 'bcd1n3'
-- Equation name is 'bcd1n3', location is LC8_A14, type is buried.
bcd1n3 = DFFE( _EQ004, GLOBAL(!key), GLOBAL( clr), VCC, VCC);
_EQ004 = bcd1n2 & !bcd1n3 & _LC1_A19 & _LC4_A24
# !bcd1n2 & bcd1n3
# bcd1n3 & !_LC4_A24
# bcd1n3 & !_LC1_A19;
-- Node name is 'led0'
-- Equation name is 'led0', type is output
led0 = _LC1_A14;
-- Node name is 'led1'
-- Equation name is 'led1', type is output
led1 = _LC1_A24;
-- Node name is 'led2'
-- Equation name is 'led2', type is output
led2 = !_LC2_A14;
-- Node name is 'led3'
-- Equation name is 'led3', type is output
led3 = _LC4_A14;
-- Node name is 'led4'
-- Equation name is 'led4', type is output
led4 = _LC3_A14;
-- Node name is 'led5'
-- Equation name is 'led5', type is output
led5 = _LC5_A24;
-- Node name is 'led6'
-- Equation name is 'led6', type is output
led6 = _LC5_A14;
-- Node name is ':18' = 'n0'
-- Equation name is 'n0', location is LC4_A19, type is buried.
n0 = DFFE(!n0, GLOBAL(!clk), VCC, VCC, VCC);
-- Node name is ':17' = 'n1'
-- Equation name is 'n1', location is LC3_A19, type is buried.
n1 = DFFE( _EQ005, GLOBAL(!clk), VCC, VCC, VCC);
_EQ005 = !_LC1_A19 & !n0 & n1
# !_LC1_A19 & n0 & !n1;
-- Node name is ':16' = 'n2'
-- Equation name is 'n2', location is LC6_A19, type is buried.
n2 = DFFE( _EQ006, GLOBAL(!clk), VCC, VCC, VCC);
_EQ006 = !_LC1_A19 & !_LC2_A19 & n2
# !_LC1_A19 & _LC2_A19 & !n2;
-- Node name is ':15' = 'n3'
-- Equation name is 'n3', location is LC5_A19, type is buried.
n3 = DFFE( _EQ007, GLOBAL(!clk), VCC, VCC, VCC);
_EQ007 = !_LC1_A19 & !n2 & n3
# !_LC1_A19 & !_LC2_A19 & n3
# !_LC1_A19 & _LC2_A19 & n2 & !n3;
-- Node name is 'output0'
-- Equation name is 'output0', type is output
output0 = bcd1n0;
-- Node name is 'output1'
-- Equation name is 'output1', type is output
output1 = bcd1n1;
-- Node name is 'output2'
-- Equation name is 'output2', type is output
output2 = bcd1n2;
-- Node name is 'output3'
-- Equation name is 'output3', type is output
output3 = bcd1n3;
-- Node name is '|LPM_ADD_SUB:83|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A19', type is buried
!_LC2_A19 = _LC2_A19~NOT;
_LC2_A19~NOT = LCELL( _EQ008);
_EQ008 = !n1
# !n0;
-- Node name is '|LPM_ADD_SUB:214|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A24', type is buried
!_LC4_A24 = _LC4_A24~NOT;
_LC4_A24~NOT = LCELL( _EQ009);
_EQ009 = !bcd1n1
# !bcd1n0;
-- Node name is ':58'
-- Equation name is '_LC1_A19', type is buried
!_LC1_A19 = _LC1_A19~NOT;
_LC1_A19~NOT = LCELL( _EQ010);
_EQ010 = !n3
# !n2
# !_LC2_A19;
-- Node name is ':189'
-- Equation name is '_LC6_A14', type is buried
!_LC6_A14 = _LC6_A14~NOT;
_LC6_A14~NOT = LCELL( _EQ011);
_EQ011 = !bcd1n3
# !bcd1n2
# !_LC4_A24;
-- Node name is ':854'
-- Equation name is '_LC2_A14', type is buried
_LC2_A14 = LCELL( _EQ012);
_EQ012 = !bcd1n0 & bcd1n1 & !bcd1n2 & !bcd1n3;
-- Node name is ':883'
-- Equation name is '_LC5_A14', type is buried
_LC5_A14 = LCELL( _EQ013);
_EQ013 = !bcd1n1 & !bcd1n2 & bcd1n3
# !bcd1n1 & bcd1n2 & !bcd1n3
# !bcd1n0 & bcd1n2 & !bcd1n3
# bcd1n1 & !bcd1n2 & !bcd1n3
# !bcd1n0 & bcd1n1 & !bcd1n3;
-- Node name is ':929'
-- Equation name is '_LC5_A24', type is buried
_LC5_A24 = LCELL( _EQ014);
_EQ014 = bcd1n3
# !bcd1n1 & bcd1n2
# !bcd1n0 & bcd1n2
# !bcd1n0 & !bcd1n1;
-- Node name is ':977'
-- Equation name is '_LC3_A14', type is buried
_LC3_A14 = LCELL( _EQ015);
_EQ015 = bcd1n2 & bcd1n3
# bcd1n1 & bcd1n3
# !bcd1n0 & bcd1n3
# !bcd1n0 & !bcd1n2
# !bcd1n0 & bcd1n1;
-- Node name is ':1025'
-- Equation name is '_LC4_A14', type is buried
_LC4_A14 = LCELL( _EQ016);
_EQ016 = bcd1n3
# !bcd1n0 & bcd1n1
# bcd1n1 & !bcd1n2
# !bcd1n0 & !bcd1n2
# bcd1n0 & !bcd1n1 & bcd1n2;
-- Node name is ':1121'
-- Equation name is '_LC1_A24', type is buried
_LC1_A24 = LCELL( _EQ017);
_EQ017 = bcd1n3
# !bcd1n2
# bcd1n0 & bcd1n1
# !bcd1n0 & !bcd1n1;
-- Node name is ':1169'
-- Equation name is '_LC1_A14', type is buried
_LC1_A14 = LCELL( _EQ018);
_EQ018 = bcd1n3
# bcd1n1
# !bcd1n0 & !bcd1n2
# bcd1n0 & bcd1n2;
Project Information e:\cpld\fenpinqi\counter.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,042K
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