fenpin.vhd

基于FPGA的分频器设计,已经通过了仿真(VHDL语言编写)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fenpin is
port (key,clr,clk,cp:in std_logic;
	  clkout:out std_logic;
	  led:buffer std_logic_vector(6 downto 0));
end fenpin;
architecture behav of counter is
	signal keyin,bcd1n:std_logic_vector(3 downto 0):="0000";
	signal m: std_logic_vector(1 downto 0):="00";
	signal count1,count2:integer;
	signal q,outclk1,outclk2:std_logic;
	signal N: integer;
begin
process(clk,m,key)
begin
	if(clk'event and clk='0') then
		if(m="11") then
			m<="00";
		else
			m<=m+'1';
		end if;
	end if;
 	if(clr='0') then
   		bcd1n<="0000";
  	else 
		if(key'event and key='0') then		
			if(m="11") then
	  			if(bcd1n="1111") then
    	      		bcd1n<="0000";
        		else
         			bcd1n<=bcd1n+1;
				end if;
     		end if;
		end if;
	end if;
end process;
process
begin
	case bcd1n is
		when "0000"=>led<="0111111";--0
		when "0001"=>led<="0000110";--1
		when "0010"=>led<="1011011";--2
		when "0011"=>led<="1001111";--3
		when "0100"=>led<="1100110";--4
		when "0101"=>led<="1101101";--5
		when "0110"=>led<="1111101";--6
		when "0111"=>led<="0000111";--7
		when "1000"=>led<="1111111";--8
		when "1001"=>led<="1101111";--9
		when "1010"=>led<="0111111";--10
		when "1011"=>led<="0111111";--
		when "1100"=>led<="0111111";
		when "1101"=>led<="0111111";
		when "1110"=>led<="0111111";
		when "1111"=>led<="0111111";
		when others=>led<="000001";
	end case;
end process;


process(keyin)
begin
case keyin is
	when "0000"=>N<=0;
	when "0001"=>N<=2;
	when "0010"=>N<=4;
	when "0011"=>N<=8;
	when "0100"=>N<=16;
	when "0101"=>N<=32;
	when "0110"=>N<=64;
	when "0111"=>N<=128;
	when "1000"=>N<=256;
	when "1001"=>N<=512;
	when "1010"=>N<=1024;
	when "1011"=>N<=2048;
	when "1100"=>N<=4096;
	when "1101"=>N<=8192;
	when "1111"=>N<=16384;
	when others=>N<=0;
end case;
end process;
process(cp)
begin
	if(cp'event and cp='1') then
	if(count1=N-1)then
	count1<=0;
	else
				count1<=count1+1;
		if count1<(integer(N/2)) then
			outclk1<='0';
		else
			outclk1<='1';
		end if;
	end if;
	end if;
end process;
process(cp)
begin
	if(cp'event and cp='0') then
	if(count2=N-1)then
			count2<=0;
	else
			count2<=count2+1;
		if count2<(integer(N/2)) then
			outclk2<='1';
		else
			outclk2<='0';
		end if;
	end if;
	end if;
q<=outclk1 and outclk2;
clkout<=q xor outclk1;
end process;

end behav;