fenpinqitop.rpt

基于FPGA的分频器设计,已经通过了仿真(VHDL语言编写)

C:       0/144(  0%)     0/ 72(  0%)     0/ 72(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
D:      22/144( 15%)     0/ 72(  0%)     1/ 72(  1%)    0/16(  0%)      1/16(  6%)     0/16(  0%)
E:      69/144( 47%)     2/ 72(  2%)    22/ 72( 30%)    0/16(  0%)      6/16( 37%)     0/16(  0%)
F:      11/144(  7%)     0/ 72(  0%)     4/ 72(  5%)    0/16(  0%)      0/16(  0%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      2/24(  8%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      2/24(  8%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
25:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
26:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
27:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
28:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
29:      4/24( 16%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
30:      5/24( 20%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
31:      3/24( 12%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
32:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
33:      3/24( 12%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
34:      3/24( 12%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
35:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
36:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                  e:\cpld\fenpinqi\fenpinqitop.rpt
fenpinqitop

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       66         CLK
INPUT        4         key


Device-Specific Information:                  e:\cpld\fenpinqi\fenpinqitop.rpt
fenpinqitop

** CLEAR SIGNALS **

Type     Fan-out       Name
INPUT        4         CLR


Device-Specific Information:                  e:\cpld\fenpinqi\fenpinqitop.rpt
fenpinqitop

** EQUATIONS **

CLK      : INPUT;
CLR      : INPUT;
key      : INPUT;

-- Node name is 'CLKout' 
-- Equation name is 'CLKout', type is output 
CLKout   =  _LC4_E32;

-- Node name is 'LEDOUT0' 
-- Equation name is 'LEDOUT0', type is output 
LEDOUT0  = !_LC6_E5;

-- Node name is 'LEDOUT1' 
-- Equation name is 'LEDOUT1', type is output 
LEDOUT1  =  VCC;

-- Node name is 'LEDOUT2' 
-- Equation name is 'LEDOUT2', type is output 
LEDOUT2  = !_LC1_E5;

-- Node name is 'LEDOUT3' 
-- Equation name is 'LEDOUT3', type is output 
LEDOUT3  = !_LC7_E5;

-- Node name is 'LEDOUT4' 
-- Equation name is 'LEDOUT4', type is output 
LEDOUT4  = !_LC8_E5;

-- Node name is 'LEDOUT5' 
-- Equation name is 'LEDOUT5', type is output 
LEDOUT5  =  _LC3_E5;

-- Node name is 'LEDOUT6' 
-- Equation name is 'LEDOUT6', type is output 
LEDOUT6  =  _LC8_E36;

-- Node name is '|COUNTER:2|:17' = '|COUNTER:2|bcd1n0' 
-- Equation name is '_LC4_E36', type is buried 
_LC4_E36 = DFFE(!_LC4_E36, GLOBAL(!key), GLOBAL( CLR),  VCC,  VCC);

-- Node name is '|COUNTER:2|:16' = '|COUNTER:2|bcd1n1' 
-- Equation name is '_LC6_E36', type is buried 
_LC6_E36 = DFFE( _EQ001, GLOBAL(!key), GLOBAL( CLR),  VCC,  VCC);
  _EQ001 = !_LC2_E28 & !_LC4_E36 &  _LC6_E36
         # !_LC2_E28 &  _LC4_E36 & !_LC6_E36;

-- Node name is '|COUNTER:2|:15' = '|COUNTER:2|bcd1n2' 
-- Equation name is '_LC5_E28', type is buried 
_LC5_E28 = DFFE( _EQ002, GLOBAL(!key), GLOBAL( CLR),  VCC,  VCC);
  _EQ002 = !_LC2_E28 &  _LC5_E28 & !_LC5_E36
         # !_LC2_E28 & !_LC5_E28 &  _LC5_E36;

-- Node name is '|COUNTER:2|:14' = '|COUNTER:2|bcd1n3' 
-- Equation name is '_LC6_E28', type is buried 
_LC6_E28 = DFFE( _EQ003, GLOBAL(!key), GLOBAL( CLR),  VCC,  VCC);
  _EQ003 = !_LC2_E28 & !_LC5_E28 &  _LC6_E28
         # !_LC2_E28 & !_LC5_E36 &  _LC6_E28
         # !_LC2_E28 &  _LC5_E28 &  _LC5_E36 & !_LC6_E28;

-- Node name is '|COUNTER:2|LPM_ADD_SUB:80|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_E36', type is buried 
!_LC5_E36 = _LC5_E36~NOT;
_LC5_E36~NOT = LCELL( _EQ004);
  _EQ004 = !_LC6_E36
         # !_LC4_E36;

-- Node name is '|COUNTER:2|:753' 
-- Equation name is '_LC3_E5', type is buried 
_LC3_E5  = LCELL( _EQ005);
  _EQ005 =  _LC5_E28
         #  _LC6_E28
         # !_LC4_E36 & !_LC6_E36
         #  _LC4_E36 &  _LC6_E36;

-- Node name is '|FENPINQI:7|:70' = '|FENPINQI:7|count10' 
-- Equation name is '_LC8_E21', type is buried 
_LC8_E21 = DFFE(!_LC8_E21, GLOBAL( CLK),  VCC,  VCC,  VCC);

-- Node name is '|FENPINQI:7|:69' = '|FENPINQI:7|count11' 
-- Equation name is '_LC4_E21', type is buried 
_LC4_E21 = DFFE( _EQ006, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ006 = !_LC1_E31 & !_LC4_E21 &  _LC8_E21
         # !_LC1_E31 &  _LC4_E21 & !_LC8_E21;

-- Node name is '|FENPINQI:7|:68' = '|FENPINQI:7|count12' 
-- Equation name is '_LC5_E21', type is buried 
_LC5_E21 = DFFE( _EQ007, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ007 = !_LC1_E31 &  _LC5_E21 & !_LC7_E21
         # !_LC1_E31 & !_LC5_E21 &  _LC7_E21;

-- Node name is '|FENPINQI:7|:67' = '|FENPINQI:7|count13' 
-- Equation name is '_LC6_E21', type is buried 
_LC6_E21 = DFFE( _EQ008, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ008 = !_LC1_E31 & !_LC5_E21 &  _LC6_E21
         # !_LC1_E31 &  _LC6_E21 & !_LC7_E21
         # !_LC1_E31 &  _LC5_E21 & !_LC6_E21 &  _LC7_E21;

-- Node name is '|FENPINQI:7|:66' = '|FENPINQI:7|count14' 
-- Equation name is '_LC1_E21', type is buried 
_LC1_E21 = DFFE( _EQ009, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ009 =  _LC1_E21 & !_LC1_E31 & !_LC2_E21
         # !_LC1_E21 & !_LC1_E31 &  _LC2_E21;

-- Node name is '|FENPINQI:7|:65' = '|FENPINQI:7|count15' 
-- Equation name is '_LC3_E21', type is buried 
_LC3_E21 = DFFE( _EQ010, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ010 = !_LC1_E21 & !_LC1_E31 &  _LC3_E21
         # !_LC1_E31 & !_LC2_E21 &  _LC3_E21
         #  _LC1_E21 & !_LC1_E31 &  _LC2_E21 & !_LC3_E21;

-- Node name is '|FENPINQI:7|:64' = '|FENPINQI:7|count16' 
-- Equation name is '_LC1_E22', type is buried 
_LC1_E22 = DFFE( _EQ011, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ011 =  _LC1_E22 & !_LC1_E31 & !_LC5_E22
         #  _LC1_E22 & !_LC1_E31 & !_LC3_E21
         # !_LC1_E22 & !_LC1_E31 &  _LC3_E21 &  _LC5_E22;

-- Node name is '|FENPINQI:7|:63' = '|FENPINQI:7|count17' 
-- Equation name is '_LC8_E22', type is buried 
_LC8_E22 = DFFE( _EQ012, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ012 = !_LC1_E31 & !_LC6_E22 &  _LC8_E22
         # !_LC1_E31 &  _LC6_E22 & !_LC8_E22;

-- Node name is '|FENPINQI:7|:62' = '|FENPINQI:7|count18' 
-- Equation name is '_LC3_E22', type is buried 
_LC3_E22 = DFFE( _EQ013, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ013 = !_LC1_E31 &  _LC3_E22 & !_LC8_E22
         # !_LC1_E31 &  _LC3_E22 & !_LC6_E22