fenpinqitop.rpt

基于FPGA的分频器设计,已经通过了仿真(VHDL语言编写)

** RESOURCE USAGE **

Logic                Column       Row                                   
Array                Interconnect Interconnect         Clears/     External  
Block   Logic Cells  Driven       Driven       Clocks  Presets   Interconnect
B23      1/ 8( 12%)   1/ 8( 12%)   0/ 8(  0%)    0/2    0/2       4/22( 18%)   
B24      8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    1/2    0/2       5/22( 22%)   
B33      3/ 8( 37%)   0/ 8(  0%)   3/ 8( 37%)    1/2    0/2       2/22(  9%)   
B34      8/ 8(100%)   2/ 8( 25%)   1/ 8( 12%)    1/2    0/2       9/22( 40%)   
D19      8/ 8(100%)   1/ 8( 12%)   3/ 8( 37%)    1/2    0/2       8/22( 36%)   
D24      8/ 8(100%)   1/ 8( 12%)   4/ 8( 50%)    1/2    0/2       6/22( 27%)   
D29      8/ 8(100%)   1/ 8( 12%)   7/ 8( 87%)    1/2    0/2       3/22( 13%)   
D30      8/ 8(100%)   3/ 8( 37%)   2/ 8( 25%)    1/2    0/2       5/22( 22%)   
D31      8/ 8(100%)   1/ 8( 12%)   2/ 8( 25%)    1/2    0/2      12/22( 54%)   
E5       8/ 8(100%)   1/ 8( 12%)   7/ 8( 87%)    0/2    0/2       4/22( 18%)   
E19      8/ 8(100%)   0/ 8(  0%)   7/ 8( 87%)    0/2    0/2      12/22( 54%)   
E20      8/ 8(100%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2      17/22( 77%)   
E21      8/ 8(100%)   0/ 8(  0%)   7/ 8( 87%)    1/2    0/2       1/22(  4%)   
E22      8/ 8(100%)   0/ 8(  0%)   5/ 8( 62%)    1/2    0/2       4/22( 18%)   
E23      7/ 8( 87%)   0/ 8(  0%)   5/ 8( 62%)    0/2    0/2      10/22( 45%)   
E24      8/ 8(100%)   2/ 8( 25%)   5/ 8( 62%)    1/2    0/2       2/22(  9%)   
E25      8/ 8(100%)   1/ 8( 12%)   5/ 8( 62%)    1/2    0/2      10/22( 45%)   
E26      1/ 8( 12%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2       2/22(  9%)   
E27      8/ 8(100%)   0/ 8(  0%)   2/ 8( 25%)    0/2    0/2      14/22( 63%)   
E28      8/ 8(100%)   1/ 8( 12%)   8/ 8(100%)    2/2    1/2       3/22( 13%)   
E29      8/ 8(100%)   0/ 8(  0%)   6/ 8( 75%)    1/2    0/2       2/22(  9%)   
E30      8/ 8(100%)   1/ 8( 12%)   5/ 8( 62%)    1/2    0/2       4/22( 18%)   
E31      8/ 8(100%)   1/ 8( 12%)   3/ 8( 37%)    0/2    0/2      17/22( 77%)   
E32      8/ 8(100%)   1/ 8( 12%)   2/ 8( 25%)    2/2    0/2      14/22( 63%)   
E33      4/ 8( 50%)   4/ 8( 50%)   0/ 8(  0%)    0/2    0/2       8/22( 36%)   
E34      8/ 8(100%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2      17/22( 77%)   
E35      8/ 8(100%)   0/ 8(  0%)   2/ 8( 25%)    0/2    0/2      15/22( 68%)   
E36      8/ 8(100%)   0/ 8(  0%)   8/ 8(100%)    1/2    1/2       3/22( 13%)   
F29      8/ 8(100%)   4/ 8( 50%)   1/ 8( 12%)    1/2    0/2       4/22( 18%)   
F32      8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    1/2    0/2       6/22( 27%)   
F36      8/ 8(100%)   1/ 8( 12%)   4/ 8( 50%)    1/2    0/2       8/22( 36%)   


Embedded             Column       Row                                   
Array     Embedded   Interconnect Interconnect         Read/      External  
Block     Cells      Driven       Driven       Clocks  Write    Interconnect


Total dedicated input pins used:                 3/6      ( 50%)
Total I/O pins used:                             8/141    (  5%)
Total logic cells used:                        224/1728   ( 12%)
Total embedded cells used:                       0/96     (  0%)
Total EABs used:                                 0/6      (  0%)
Average fan-in:                                 3.39/4    ( 84%)
Total fan-in:                                 761/6912    ( 11%)

Total input pins required:                       3
Total input I/O cell registers required:         0
Total output pins required:                      8
Total output I/O cell registers required:        0
Total buried I/O cell registers required:        0
Total bidirectional pins required:               0
Total reserved pins required                     0
Total logic cells required:                    224
Total flipflops required:                       70
Total packed registers required:                 0
Total logic cells in carry chains:               0
Total number of carry chains:                    0
Total logic cells in cascade chains:             0
Total number of cascade chains:                  0
Total single-pin Clock Enables required:         0
Total single-pin Output Enables required:        0

Synthesized logic cells:                        51/1728   (  2%)

Logic Cell and Embedded Cell Counts

Column:  01  02  03  04  05  06  07  08  09  10  11  12  13  14  15  16  17  18  EA  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  Total(LC/EC)
 A:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  
 B:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1   8   0   0   0   0   0   0   0   0   3   8   0   0     20/0  
 C:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  
 D:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   8   0   0   0   0   8   0   0   0   0   8   8   8   0   0   0   0   0     40/0  
 E:      0   0   0   0   8   0   0   0   0   0   0   0   0   0   0   0   0   0   0   8   8   8   8   7   8   8   1   8   8   8   8   8   8   4   8   8   8    140/0  
 F:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   8   0   0   8   0   0   0   8     24/0  

Total:   0   0   0   0   8   0   0   0   0   0   0   0   0   0   0   0   0   0   0  16   8   8   8   8  24   8   1   8   8  24  16  16  16   7  16   8  16    224/0  



Device-Specific Information:                  e:\cpld\fenpinqi\fenpinqitop.rpt
fenpinqitop

** INPUTS **

                                                    Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
 183      -     -    -    --      INPUT  G          ^    0    0    0    0  CLK
  78      -     -    -    --      INPUT  G          ^    0    0    0    0  CLR
  79      -     -    -    --      INPUT  G          ^    0    0    0    0  key


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:                  e:\cpld\fenpinqi\fenpinqitop.rpt
fenpinqitop

** OUTPUTS **

       Fed By Fed By                                Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
  38      -     -    E    --     OUTPUT                 0    1    0    0  CLKout
  40      -     -    E    --     OUTPUT                 0    1    0    0  LEDOUT0
  31      -     -    D    --     OUTPUT                 0    0    0    0  LEDOUT1
  36      -     -    E    --     OUTPUT                 0    1    0    0  LEDOUT2
 100      -     -    -    05     OUTPUT                 0    1    0    0  LEDOUT3
 119      -     -    E    --     OUTPUT                 0    1    0    0  LEDOUT4
 121      -     -    E    --     OUTPUT                 0    1    0    0  LEDOUT5
 120      -     -    E    --     OUTPUT                 0    1    0    0  LEDOUT6


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable


Device-Specific Information:                  e:\cpld\fenpinqi\fenpinqitop.rpt
fenpinqitop

** BURIED LOGIC **

                                                    Fan-In    Fan-Out
 IOC     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      5     -    E    36        OR2        !       0    2    0    6  |COUNTER:2|LPM_ADD_SUB:80|addcore:adder|:55
   -      6     -    E    28       DFFE   +            0    3    0   18  |COUNTER:2|bcd1n3 (|COUNTER:2|:14)
   -      5     -    E    28       DFFE   +            0    2    0   19  |COUNTER:2|bcd1n2 (|COUNTER:2|:15)
   -      6     -    E    36       DFFE   +            0    2    0   15  |COUNTER:2|bcd1n1 (|COUNTER:2|:16)
   -      4     -    E    36       DFFE   +            0    0    0   16  |COUNTER:2|bcd1n0 (|COUNTER:2|:17)
   -      3     -    E    05        OR2                0    4    1    0  |COUNTER:2|:753
   -      7     -    E    21       AND2                0    2    0    3  |FENPINQI:7|LPM_ADD_SUB:3906|addcore:adder|:167
   -      2     -    E    21       AND2                0    3    0    4  |FENPINQI:7|LPM_ADD_SUB:3906|addcore:adder|:175
   -      5     -    E    22       AND2                0    2    0    1  |FENPINQI:7|LPM_ADD_SUB:3906|addcore:adder|:179
   -      6     -    E    22       AND2                0    4    0    4  |FENPINQI:7|LPM_ADD_SUB:3906|addcore:adder|:187
   -      7     -    E    22       AND2                0    2    0    1  |FENPINQI:7|LPM_ADD_SUB:3906|addcore:adder|:191
   -      2     -    E    22       AND2                0    4    0    3  |FENPINQI:7|LPM_ADD_SUB:3906|addcore:adder|:199
   -      3     -    E    24       AND2                0    3    0    4  |FENPINQI:7|LPM_ADD_SUB:3906|addcore:adder|:207
   -      5     -    E    24       AND2                0    2    0    1  |FENPINQI:7|LPM_ADD_SUB:3906|addcore:adder|:211
   -      1     -    E    24       AND2                0    4    0    4  |FENPINQI:7|LPM_ADD_SUB:3906|addcore:adder|:219
   -      8     -    D    29       AND2                0    3    0    1  |FENPINQI:7|LPM_ADD_SUB:3906|addcore:adder|:227
   -      2     -    D    29       AND2                0    4    0    3  |FENPINQI:7|LPM_ADD_SUB:3906|addcore:adder|:231
   -      2     -    D    31       AND2                0    3    0    4  |FENPINQI:7|LPM_ADD_SUB:3906|addcore:adder|:239
   -      1     -    D    24       AND2                0    2    0    1  |FENPINQI:7|LPM_ADD_SUB:3906|addcore:adder|:243
   -      2     -    D    24       AND2                0    4    0    4  |FENPINQI:7|LPM_ADD_SUB:3906|addcore:adder|:251
   -      1     -    D    29       AND2                0    2    0    1  |FENPINQI:7|LPM_ADD_SUB:3906|addcore:adder|:255
   -      7     -    D    19       AND2                0    4    0    3  |FENPINQI:7|LPM_ADD_SUB:3906|addcore:adder|:263
   -      2     -    D    19       AND2                0    3    0    3  |FENPINQI:7|LPM_ADD_SUB:3906|addcore:adder|:271
   -      3     -    D    30       AND2                0    3    0    2  |FENPINQI:7|LPM_ADD_SUB:3906|addcore:adder|:279
   -      1     -    E    26       AND2        !       0    2    0    4  |FENPINQI:7|LPM_ADD_SUB:4979|addcore:adder|pcarry2
   -      3     -    E    19       AND2        !       0    2    0    3  |FENPINQI:7|LPM_ADD_SUB:4979|addcore:adder|pcarry3
   -      8     -    E    19       AND2        !       0    2    0    4  |FENPINQI:7|LPM_ADD_SUB:4979|addcore:adder|pcarry4
   -      7     -    E    19       AND2        !       0    3    0    5  |FENPINQI:7|LPM_ADD_SUB:4979|addcore:adder|pcarry6
   -      2     -    E    23       AND2        !       0    3    0    5  |FENPINQI:7|LPM_ADD_SUB:4979|addcore:adder|pcarry8
   -      4     -    E    31       AND2        !       0    3    0    3  |FENPINQI:7|LPM_ADD_SUB:4979|addcore:adder|pcarry10
   -      1     -    E    25       AND2        !       0    2    0    5  |FENPINQI:7|LPM_ADD_SUB:4979|addcore:adder|pcarry11
   -      3     -    E    33       AND2        !       0    3    0    3  |FENPINQI:7|LPM_ADD_SUB:4979|addcore:adder|pcarry13
   -      6     -    E    33       AND2        !       0    2    0   16  |FENPINQI:7|LPM_ADD_SUB:4979|addcore:adder|pcarry14
   -      2     -    E    25       AND2                0    2    0    3  |FENPINQI:7|LPM_ADD_SUB:5273|addcore:adder|:167
   -      2     -    E    29       AND2                0    3    0    4  |FENPINQI:7|LPM_ADD_SUB:5273|addcore:adder|:175
   -      4     -    E    29       AND2                0    2    0    1  |FENPINQI:7|LPM_ADD_SUB:5273|addcore:adder|:179
   -      1     -    E    29       AND2                0    4    0    4  |FENPINQI:7|LPM_ADD_SUB:5273|addcore:adder|:187
   -      5     -    E    30       AND2                0    2    0    1  |FENPINQI:7|LPM_ADD_SUB:5273|addcore:adder|:191
   -      6     -    E    30       AND2                0    4    0    4  |FENPINQI:7|LPM_ADD_SUB:5273|addcore:adder|:199
   -      7     -    E    30       AND2                0    2    0    1  |FENPINQI:7|LPM_ADD_SUB:5273|addcore:adder|:203
   -      1     -    E    30       AND2                0    4    0    2  |FENPINQI:7|LPM_ADD_SUB:5273|addcore:adder|:211
   -      4     -    F    36       AND2                0    2    0    4  |FENPINQI:7|LPM_ADD_SUB:5273|addcore:adder|:215
   -      5     -    F    36       AND2                0    3    0    1  |FENPINQI:7|LPM_ADD_SUB:5273|addcore:adder|:223
   -      2     -    F    36       AND2                0    4    0    4  |FENPINQI:7|LPM_ADD_SUB:5273|addcore:adder|:227
   -      6     -    F    32       AND2                0    3    0    1  |FENPINQI:7|LPM_ADD_SUB:5273|addcore:adder|:235
   -      8     -    F    32       AND2                0    4    0    3  |FENPINQI:7|LPM_ADD_SUB:5273|addcore:adder|:239
   -      6     -    F    29       AND2                0    3    0    3  |FENPINQI:7|LPM_ADD_SUB:5273|addcore:adder|:247
   -      1     -    F    29       AND2                0    3    0    4  |FENPINQI:7|LPM_ADD_SUB:5273|addcore:adder|:255
   -      6     -    B    24       AND2                0    3    0    1  |FENPINQI:7|LPM_ADD_SUB:5273|addcore:adder|:263