test.fit

基于FPGA的分频器设计,已经通过了仿真(VHDL语言编写)

-- MAX+plus II Compiler Fit File      
-- Version 10.2 07/10/2002            
-- Compiled: 10/21/2006 23:05:32      

-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "test"
BEGIN

    DEVICE = "EP1K30QC208-2";

    "clk"                          : INPUT_PIN  = 79     ;
    "clr"                          : INPUT_PIN  = 46     ;
    "key"                          : INPUT_PIN  = 45     ;
    "data0"                        : OUTPUT_PIN = 19     ;
    "data1"                        : OUTPUT_PIN = 24     ;
    "data2"                        : OUTPUT_PIN = 25     ;
    "data3"                        : OUTPUT_PIN = 26     ;
    "led0"                         : OUTPUT_PIN = 10     ;
    "led1"                         : OUTPUT_PIN = 11     ;
    "led2"                         : OUTPUT_PIN = 12     ;
    "led3"                         : OUTPUT_PIN = 13     ;
    "led4"                         : OUTPUT_PIN = 14     ;
    "led5"                         : OUTPUT_PIN = 15     ;
    "led6"                         : OUTPUT_PIN = 16     ;
    "|COUNTER:6|LPM_ADD_SUB:156|addcore:adder|:55" : LOCATION   = LC6_F20;
    "|COUNTER:6|:15"               : LOCATION   = LC2_F26;  -- |COUNTER:6|n1
    "|COUNTER:6|:16"               : LOCATION   = LC3_F26;  -- |COUNTER:6|n0
    "|COUNTER:6|:17"               : LOCATION   = LC1_F20;  -- |COUNTER:6|bcd1n3
    "|COUNTER:6|:18"               : LOCATION   = LC4_F20;  -- |COUNTER:6|bcd1n2
    "|COUNTER:6|:19"               : LOCATION   = LC7_F20;  -- |COUNTER:6|bcd1n1
    "|COUNTER:6|:20"               : LOCATION   = LC3_F20;  -- |COUNTER:6|bcd1n0
    "|COUNTER:6|:48"               : LOCATION   = LC1_F26;
    "|COUNTER:6|~209~1"            : LOCATION   = LC8_F20;
    "|COUNTER:6|:792"              : LOCATION   = LC2_B23;
    "|COUNTER:6|:821"              : LOCATION   = LC1_B23;
    "|COUNTER:6|:867"              : LOCATION   = LC7_B27;
    "|COUNTER:6|:915"              : LOCATION   = LC5_B23;
    "|COUNTER:6|:963"              : LOCATION   = LC2_F20;
    "|COUNTER:6|:1059"             : LOCATION   = LC7_B23;
    "|COUNTER:6|:1107"             : LOCATION   = LC5_F20;

END;

INTERNAL_INFO "test"
BEGIN
	DEVICE = EP1K30QC208-2;
    OD5P79  : LORAX = "1:FB5->LC2_F26,->LC3_F26|";
    OH4R5P46 : LORAX = "1:G64R5,PA15R5C19->LC1_F20,->LC4_F20,->LC7_F20,->LC3_F20|";
    LC1_F20 : LORAX = "1:MSW1R5C18,V5C18|2:HHR16R1|3:PA5R1C22->LC2_B23,->LC1_B23,->LC5_B23,->LC7_B23|,3:PA5R1C26->LC7_B27||,2:HHR16R3->OH1R3P26||";
    LC4_F20 : LORAX = "1:MSW0R5C18,V2C18|2:HHR23R1|3:PA1R1C22->LC2_B23,->LC1_B23,->LC5_B23,->LC7_B23|,3:PA1R1C26->LC7_B27||,2:HHR23R3->OH0R3P25||";
    LC7_F20 : LORAX = "1:MSW6R5C19,V20C19|2:HHR37R1|3:PA7R1C22->LC2_B23,->LC1_B23,->LC5_B23,->LC7_B23|,3:PA7R1C26->LC7_B27||,2:HHR37R2->OH6R2P24||";
    LC3_F20 : LORAX = "1:MSW3R5C18,V11C18|2:HHR25R1|3:PA3R1C22->LC2_B23,->LC1_B23,->LC5_B23,->LC7_B23|,3:PA3R1C26->LC7_B27||,2:HHR25R2->OH3R2P19||";
    LC1_F26 : LORAX = "1:MSW0R5C25,HHR29R5,PA7R5C19->LC1_F20,->LC4_F20,->LC7_F20,->LC3_F20,->LC8_F20|";
    LC2_B23 : LORAX = "1:MSW1R1C22,G38R1->OH1R1P12|";
    LC1_B23 : LORAX = "1:MSW0R1C22,V2C22,HHR18R2->OH0R2P16|";
    LC7_B27 : LORAX = "1:MSW6R1C27,HHR44R1->OH6R1P15|";
    LC5_B23 : LORAX = "1:MSW4R1C22,HHR64R1->OH4R1P14|";
    LC2_F20 : LORAX = "1:MSW2R5C18,V8C18,HHR32R1->OH2R1P13|";
    LC7_B23 : LORAX = "1:MSW6R1C23,V20C23,HHR46R0->OH6R0P11|";
    LC5_F20 : LORAX = "1:MSW4R5C19,V13C19,HHR43R0->OH4R0P10|";
    OH2R5P45 : LORAX = "1:G58R5,PA4R5C19->LC1_F20,->LC4_F20,->LC7_F20,->LC3_F20|";
	LC6_F20 : LORAX2 = "X, X, LC3_F20, LC7_F20";
	LC2_F26 : LORAX2 = "X, LC3_F26, LC2_F26, LC1_F26";
	LC3_F26 : LORAX2 = "X, X, X, LC3_F26";
	LC1_F20 : LORAX2 = "LC1_F26, LC6_F20, LC1_F20, LC4_F20";
	LC4_F20 : LORAX2 = "X, LC1_F26, LC6_F20, LC4_F20";
	LC7_F20 : LORAX2 = "LC1_F26, LC8_F20, LC7_F20, LC3_F20";
	LC3_F20 : LORAX2 = "X, X, LC1_F26, LC3_F20";
	LC1_F26 : LORAX2 = "X, X, LC3_F26, LC2_F26";
	LC8_F20 : LORAX2 = "LC1_F26, LC6_F20, LC1_F20, LC4_F20";
	LC2_B23 : LORAX2 = "LC7_F20, LC3_F20, LC1_F20, LC4_F20";
	LC1_B23 : LORAX2 = "LC7_F20, LC3_F20, LC1_F20, LC4_F20";
	LC7_B27 : LORAX2 = "LC1_F20, LC3_F20, LC4_F20, LC7_F20";
	LC5_B23 : LORAX2 = "LC1_F20, LC3_F20, LC4_F20, LC7_F20";
	LC2_F20 : LORAX2 = "LC1_F20, LC3_F20, LC4_F20, LC7_F20";
	LC7_B23 : LORAX2 = "LC7_F20, LC3_F20, LC1_F20, LC4_F20";
	LC5_F20 : LORAX2 = "LC7_F20, LC3_F20, LC1_F20, LC4_F20";
END;