📄 fenpinqi.rpt
字号:
- 3 - C 29 DFFE + 0 3 0 1 outclk1 (:71)
- 3 - C 30 DFFE + 0 3 0 2 count231 (:72)
- 2 - C 30 DFFE + 0 2 0 3 count230 (:73)
- 1 - C 36 DFFE + 0 3 0 3 count229 (:74)
- 3 - C 36 DFFE + 0 3 0 4 count228 (:75)
- 8 - C 36 DFFE + 0 2 0 5 count227 (:76)
- 1 - C 33 DFFE + 0 3 0 3 count226 (:77)
- 6 - C 33 DFFE + 0 2 0 4 count225 (:78)
- 4 - C 33 DFFE + 0 3 0 3 count224 (:79)
- 5 - C 33 DFFE + 0 2 0 4 count223 (:80)
- 3 - C 26 DFFE + 0 2 0 3 count222 (:81)
- 8 - C 26 DFFE + 0 3 0 3 count221 (:82)
- 5 - C 26 DFFE + 0 3 0 4 count220 (:83)
- 1 - C 26 DFFE + 0 2 0 5 count219 (:84)
- 7 - C 28 DFFE + 0 3 0 3 count218 (:85)
- 5 - C 28 DFFE + 0 2 0 4 count217 (:86)
- 6 - C 31 DFFE + 0 2 0 3 count216 (:87)
- 1 - C 28 DFFE + 0 3 0 4 count215 (:88)
- 6 - C 28 DFFE + 0 2 0 5 count214 (:89)
- 7 - C 21 DFFE + 0 3 0 3 count213 (:90)
- 4 - C 21 DFFE + 0 2 0 4 count212 (:91)
- 6 - C 21 DFFE + 0 2 0 3 count211 (:92)
- 1 - C 21 DFFE + 0 3 0 3 count210 (:93)
- 2 - C 31 DFFE + 0 3 0 4 count29 (:94)
- 8 - C 31 DFFE + 0 2 0 5 count28 (:95)
- 5 - C 34 DFFE + 0 3 0 3 count27 (:96)
- 7 - C 34 DFFE + 0 2 0 4 count26 (:97)
- 3 - C 34 DFFE + 0 2 0 3 count25 (:98)
- 8 - C 34 DFFE + 0 3 0 4 count24 (:99)
- 4 - C 34 DFFE + 0 2 0 5 count23 (:100)
- 3 - C 35 DFFE + 0 3 0 3 count22 (:101)
- 6 - C 35 DFFE + 0 2 0 4 count21 (:102)
- 7 - C 35 DFFE + 0 0 0 5 count20 (:103)
- 8 - C 29 DFFE + 0 3 0 1 outclk2 (:104)
- 5 - C 19 OR2 ! 4 0 0 5 :1671
- 3 - C 19 OR2 ! 4 0 0 5 :1683
- 4 - C 19 OR2 ! 4 0 0 7 :1695
- 6 - C 19 OR2 ! 4 0 0 5 :1707
- 5 - B 36 OR2 ! 4 0 0 7 :1719
- 1 - B 26 OR2 ! 4 0 0 6 :1731
- 1 - B 36 OR2 ! 4 0 0 5 :1743
- 7 - B 36 OR2 ! 4 0 0 5 :1755
- 6 - B 36 OR2 ! 4 0 0 7 :1767
- 2 - B 36 OR2 ! 4 0 0 6 :1779
- 4 - B 36 OR2 ! 4 0 0 5 :1791
- 3 - B 36 OR2 ! 4 0 0 7 :1803
- 4 - B 26 OR2 ! 4 0 0 9 :1815
- 8 - B 36 OR2 ! 4 0 0 5 :2648
- 4 - F 24 OR2 s 0 4 0 1 ~3613~1
- 3 - F 31 OR2 s 0 4 0 1 ~3613~2
- 1 - C 24 OR2 s 0 4 0 1 ~3613~3
- 1 - F 28 OR2 s 0 4 0 1 ~3613~4
- 3 - F 24 OR2 s 0 4 0 1 ~3613~5
- 5 - F 29 OR2 s 0 4 0 1 ~3613~6
- 8 - F 19 OR2 s 0 4 0 1 ~3613~7
- 7 - F 24 OR2 s 0 4 0 1 ~3613~8
- 7 - F 23 OR2 s 0 4 0 1 ~3613~9
- 2 - F 33 OR2 s 0 4 0 1 ~3613~10
- 3 - F 33 OR2 s 0 4 0 1 ~3613~11
- 5 - F 33 OR2 s 0 4 0 1 ~3613~12
- 6 - F 33 OR2 s 0 4 0 1 ~3613~13
- 4 - F 33 OR2 s 0 4 0 1 ~3613~14
- 5 - F 36 OR2 s 0 4 0 1 ~3613~15
- 4 - F 23 OR2 ! 0 4 0 32 :3613
- 5 - C 24 OR2 ! 0 4 0 1 :3636
- 6 - F 31 OR2 ! 0 4 0 1 :3638
- 1 - F 24 OR2 ! 0 4 0 1 :3639
- 6 - F 24 OR2 ! 0 3 0 1 :3640
- 1 - C 22 OR2 ! 0 4 0 1 :3642
- 5 - F 23 OR2 ! 0 4 0 1 :3643
- 6 - F 23 OR2 ! 0 3 0 1 :3644
- 3 - F 19 OR2 ! 0 4 0 1 :3645
- 2 - F 34 OR2 s 0 3 0 1 ~4037~1
- 1 - F 36 OR2 s 0 3 0 1 ~4037~2
- 1 - F 33 OR2 s 0 4 0 1 ~4037~3
- 3 - F 34 OR2 s 0 4 0 1 ~4037~4
- 4 - F 28 OR2 s 0 4 0 1 ~4037~5
- 1 - F 34 OR2 s 0 4 0 1 ~4037~6
- 2 - C 29 OR2 ! 0 4 0 1 :4037
- 1 - C 29 OR2 ! 0 3 0 1 :4134
- 1 - F 35 OR2 ! 0 3 0 1 :4139
- 8 - F 35 OR2 ! 0 3 0 1 :4144
- 7 - F 35 OR2 ! 0 3 0 1 :4149
- 6 - F 35 OR2 ! 0 3 0 1 :4154
- 5 - F 35 OR2 ! 0 3 0 1 :4159
- 4 - F 35 OR2 ! 0 3 0 1 :4164
- 3 - F 35 OR2 ! 0 3 0 1 :4169
- 2 - F 35 OR2 ! 0 3 0 1 :4174
- 1 - F 19 OR2 ! 0 3 0 1 :4179
- 7 - F 19 OR2 ! 0 4 0 1 :4184
- 6 - F 19 OR2 s 0 3 0 1 ~4189~1
- 2 - C 24 OR2 s 0 4 0 1 ~4980~1
- 1 - C 19 OR2 s 0 4 0 1 ~4980~2
- 2 - C 19 OR2 s 0 4 0 1 ~4980~3
- 4 - C 30 OR2 s 0 4 0 1 ~4980~4
- 5 - C 30 OR2 s 0 4 0 1 ~4980~5
- 8 - C 22 OR2 s 0 4 0 1 ~4980~6
- 1 - C 35 OR2 s 0 4 0 1 ~4980~7
- 4 - C 35 OR2 s 0 4 0 1 ~4980~8
- 2 - C 22 OR2 s 0 4 0 1 ~4980~9
- 4 - C 26 OR2 s 0 4 0 1 ~4980~10
- 4 - C 28 OR2 s 0 4 0 1 ~4980~11
- 6 - C 30 OR2 s 0 4 0 1 ~4980~12
- 7 - C 30 OR2 s 0 4 0 1 ~4980~13
- 8 - C 30 OR2 s 0 4 0 1 ~4980~14
- 8 - C 33 OR2 s 0 4 0 1 ~4980~15
- 1 - C 30 OR2 ! 0 4 0 32 :4980
- 8 - C 19 OR2 ! 0 4 0 1 :5003
- 7 - C 19 OR2 ! 0 4 0 1 :5005
- 7 - C 24 OR2 ! 0 3 0 1 :5006
- 1 - C 31 OR2 ! 0 3 0 1 :5007
- 6 - C 22 OR2 ! 0 4 0 1 :5009
- 4 - C 22 OR2 ! 0 3 0 1 :5010
- 5 - C 22 OR2 ! 0 3 0 1 :5011
- 2 - C 20 OR2 ! 0 4 0 1 :5012
- 3 - C 33 AND2 s 0 4 0 1 ~5404~1
- 7 - C 36 AND2 s 0 4 0 1 ~5404~2
- 3 - C 31 AND2 s 0 3 0 1 ~5404~3
- 5 - C 36 AND2 s 0 4 0 1 ~5404~4
- 6 - C 26 AND2 s 0 3 0 1 ~5404~5
- 6 - C 29 AND2 s 0 4 0 1 ~5404~6
- 7 - C 29 OR2 0 4 0 1 :5404
- 5 - C 29 OR2 0 3 0 1 :5501
- 2 - C 27 OR2 0 3 0 1 :5506
- 8 - C 27 OR2 0 3 0 1 :5511
- 7 - C 27 OR2 0 3 0 1 :5516
- 6 - C 27 OR2 0 3 0 1 :5521
- 5 - C 27 OR2 0 3 0 1 :5526
- 4 - C 27 OR2 0 3 0 1 :5531
- 3 - C 27 OR2 0 3 0 1 :5536
- 1 - C 27 OR2 0 3 0 1 :5541
- 4 - C 15 OR2 0 3 0 1 :5546
- 5 - C 35 OR2 0 4 0 1 :5551
- 8 - C 35 OR2 s 0 3 0 1 ~5556~1
- 4 - C 29 AND2 0 2 1 0 :6120
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\cpld\fenpinqi\fenpinqi.rpt
fenpinqi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 60/144( 41%) 0/ 72( 0%) 21/ 72( 29%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 48/144( 33%) 0/ 72( 0%) 19/ 72( 26%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 8/24( 33%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\cpld\fenpinqi\fenpinqi.rpt
fenpinqi
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 66 clk
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