test.rpt

基于FPGA的分频器设计,已经通过了仿真(VHDL语言编写)

-- Equation name is 'led0', type is output 
led0     =  _LC5_F20;

-- Node name is 'led1' 
-- Equation name is 'led1', type is output 
led1     =  _LC7_B23;

-- Node name is 'led2' 
-- Equation name is 'led2', type is output 
led2     = !_LC2_B23;

-- Node name is 'led3' 
-- Equation name is 'led3', type is output 
led3     =  _LC2_F20;

-- Node name is 'led4' 
-- Equation name is 'led4', type is output 
led4     =  _LC5_B23;

-- Node name is 'led5' 
-- Equation name is 'led5', type is output 
led5     =  _LC7_B27;

-- Node name is 'led6' 
-- Equation name is 'led6', type is output 
led6     =  _LC1_B23;

-- Node name is '|COUNTER:6|:20' = '|COUNTER:6|bcd1n0' 
-- Equation name is '_LC3_F20', type is buried 
_LC3_F20 = DFFE( _EQ001, !key,  clr,  VCC,  VCC);
  _EQ001 = !_LC1_F26 &  _LC3_F20
         #  _LC1_F26 & !_LC3_F20;

-- Node name is '|COUNTER:6|:19' = '|COUNTER:6|bcd1n1' 
-- Equation name is '_LC7_F20', type is buried 
_LC7_F20 = DFFE( _EQ002, !key,  clr,  VCC,  VCC);
  _EQ002 = !_LC3_F20 &  _LC7_F20 &  _LC8_F20
         #  _LC3_F20 & !_LC7_F20 &  _LC8_F20
         # !_LC1_F26 &  _LC7_F20;

-- Node name is '|COUNTER:6|:18' = '|COUNTER:6|bcd1n2' 
-- Equation name is '_LC4_F20', type is buried 
_LC4_F20 = DFFE( _EQ003, !key,  clr,  VCC,  VCC);
  _EQ003 =  _LC4_F20 & !_LC6_F20
         #  _LC1_F26 & !_LC4_F20 &  _LC6_F20
         # !_LC1_F26 &  _LC4_F20;

-- Node name is '|COUNTER:6|:17' = '|COUNTER:6|bcd1n3' 
-- Equation name is '_LC1_F20', type is buried 
_LC1_F20 = DFFE( _EQ004, !key,  clr,  VCC,  VCC);
  _EQ004 = !_LC1_F20 &  _LC1_F26 &  _LC4_F20 &  _LC6_F20
         #  _LC1_F20 & !_LC4_F20
         #  _LC1_F20 & !_LC6_F20
         #  _LC1_F20 & !_LC1_F26;

-- Node name is '|COUNTER:6|LPM_ADD_SUB:156|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_F20', type is buried 
!_LC6_F20 = _LC6_F20~NOT;
_LC6_F20~NOT = LCELL( _EQ005);
  _EQ005 = !_LC7_F20
         # !_LC3_F20;

-- Node name is '|COUNTER:6|:16' = '|COUNTER:6|n0' 
-- Equation name is '_LC3_F26', type is buried 
_LC3_F26 = DFFE(!_LC3_F26, GLOBAL(!clk),  VCC,  VCC,  VCC);

-- Node name is '|COUNTER:6|:15' = '|COUNTER:6|n1' 
-- Equation name is '_LC2_F26', type is buried 
_LC2_F26 = DFFE( _EQ006, GLOBAL(!clk),  VCC,  VCC,  VCC);
  _EQ006 = !_LC1_F26 &  _LC2_F26 & !_LC3_F26
         # !_LC1_F26 & !_LC2_F26 &  _LC3_F26;

-- Node name is '|COUNTER:6|:48' 
-- Equation name is '_LC1_F26', type is buried 
!_LC1_F26 = _LC1_F26~NOT;
_LC1_F26~NOT = LCELL( _EQ007);
  _EQ007 = !_LC2_F26
         # !_LC3_F26;

-- Node name is '|COUNTER:6|~209~1' 
-- Equation name is '_LC8_F20', type is buried 
-- synthesized logic cell 
_LC8_F20 = LCELL( _EQ008);
  _EQ008 = !_LC1_F20 &  _LC1_F26
         #  _LC1_F26 & !_LC4_F20
         #  _LC1_F26 & !_LC6_F20;

-- Node name is '|COUNTER:6|:792' 
-- Equation name is '_LC2_B23', type is buried 
_LC2_B23 = LCELL( _EQ009);
  _EQ009 = !_LC1_F20 & !_LC3_F20 & !_LC4_F20 &  _LC7_F20;

-- Node name is '|COUNTER:6|:821' 
-- Equation name is '_LC1_B23', type is buried 
_LC1_B23 = LCELL( _EQ010);
  _EQ010 =  _LC1_F20 & !_LC4_F20 & !_LC7_F20
         # !_LC1_F20 &  _LC4_F20 & !_LC7_F20
         # !_LC1_F20 & !_LC3_F20 &  _LC4_F20
         # !_LC1_F20 & !_LC4_F20 &  _LC7_F20
         # !_LC1_F20 & !_LC3_F20 &  _LC7_F20;

-- Node name is '|COUNTER:6|:867' 
-- Equation name is '_LC7_B27', type is buried 
_LC7_B27 = LCELL( _EQ011);
  _EQ011 =  _LC1_F20
         #  _LC4_F20 & !_LC7_F20
         # !_LC3_F20 &  _LC4_F20
         # !_LC3_F20 & !_LC7_F20;

-- Node name is '|COUNTER:6|:915' 
-- Equation name is '_LC5_B23', type is buried 
_LC5_B23 = LCELL( _EQ012);
  _EQ012 =  _LC1_F20 &  _LC4_F20
         #  _LC1_F20 &  _LC7_F20
         #  _LC1_F20 & !_LC3_F20
         # !_LC3_F20 & !_LC4_F20
         # !_LC3_F20 &  _LC7_F20;

-- Node name is '|COUNTER:6|:963' 
-- Equation name is '_LC2_F20', type is buried 
_LC2_F20 = LCELL( _EQ013);
  _EQ013 =  _LC1_F20
         # !_LC3_F20 &  _LC7_F20
         # !_LC4_F20 &  _LC7_F20
         # !_LC3_F20 & !_LC4_F20
         #  _LC3_F20 &  _LC4_F20 & !_LC7_F20;

-- Node name is '|COUNTER:6|:1059' 
-- Equation name is '_LC7_B23', type is buried 
_LC7_B23 = LCELL( _EQ014);
  _EQ014 =  _LC1_F20
         # !_LC4_F20
         #  _LC3_F20 &  _LC7_F20
         # !_LC3_F20 & !_LC7_F20;

-- Node name is '|COUNTER:6|:1107' 
-- Equation name is '_LC5_F20', type is buried 
_LC5_F20 = LCELL( _EQ015);
  _EQ015 =  _LC1_F20
         #  _LC7_F20
         # !_LC3_F20 & !_LC4_F20
         #  _LC3_F20 &  _LC4_F20;



Project Information                                  e:\cpld\fenpinqi\test.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:05


Memory Allocated
-----------------

Peak memory allocated during compilation  = 26,482K