📄 test.rpt
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Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 16
Total flipflops required: 6
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 1/1728 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 1 0 0 0 0 0 0 0 0 0 5/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 11/0
Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 4 0 0 3 1 0 0 0 0 0 0 0 0 0 16/0
Device-Specific Information: e:\cpld\fenpinqi\test.rpt
test
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
79 - - - -- INPUT G ^ 0 0 0 0 clk
46 - - F -- INPUT ^ 0 0 0 4 clr
45 - - F -- INPUT ^ 0 0 0 4 key
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\cpld\fenpinqi\test.rpt
test
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
19 - - C -- OUTPUT 0 1 0 0 data0
24 - - C -- OUTPUT 0 1 0 0 data1
25 - - D -- OUTPUT 0 1 0 0 data2
26 - - D -- OUTPUT 0 1 0 0 data3
10 - - A -- OUTPUT 0 1 0 0 led0
11 - - A -- OUTPUT 0 1 0 0 led1
12 - - B -- OUTPUT 0 1 0 0 led2
13 - - B -- OUTPUT 0 1 0 0 led3
14 - - B -- OUTPUT 0 1 0 0 led4
15 - - B -- OUTPUT 0 1 0 0 led5
16 - - C -- OUTPUT 0 1 0 0 led6
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\cpld\fenpinqi\test.rpt
test
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - F 20 OR2 ! 0 2 0 3 |COUNTER:6|LPM_ADD_SUB:156|addcore:adder|:55
- 2 - F 26 DFFE + 0 2 0 1 |COUNTER:6|n1 (|COUNTER:6|:15)
- 3 - F 26 DFFE + 0 0 0 2 |COUNTER:6|n0 (|COUNTER:6|:16)
- 1 - F 20 DFFE 2 3 1 8 |COUNTER:6|bcd1n3 (|COUNTER:6|:17)
- 4 - F 20 DFFE 2 2 1 9 |COUNTER:6|bcd1n2 (|COUNTER:6|:18)
- 7 - F 20 DFFE 2 3 1 8 |COUNTER:6|bcd1n1 (|COUNTER:6|:19)
- 3 - F 20 DFFE 2 1 1 9 |COUNTER:6|bcd1n0 (|COUNTER:6|:20)
- 1 - F 26 OR2 ! 0 2 0 6 |COUNTER:6|:48
- 8 - F 20 OR2 s 0 4 0 1 |COUNTER:6|~209~1
- 2 - B 23 AND2 0 4 1 0 |COUNTER:6|:792
- 1 - B 23 OR2 0 4 1 0 |COUNTER:6|:821
- 7 - B 27 OR2 0 4 1 0 |COUNTER:6|:867
- 5 - B 23 OR2 0 4 1 0 |COUNTER:6|:915
- 2 - F 20 OR2 0 4 1 0 |COUNTER:6|:963
- 7 - B 23 OR2 0 4 1 0 |COUNTER:6|:1059
- 5 - F 20 OR2 0 4 1 0 |COUNTER:6|:1107
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\cpld\fenpinqi\test.rpt
test
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 2/ 72( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 1/144( 0%) 0/ 72( 0%) 7/ 72( 9%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 3/ 72( 4%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 2/ 72( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 2/144( 1%) 0/ 72( 0%) 1/ 72( 1%) 2/16( 12%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\cpld\fenpinqi\test.rpt
test
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 key
INPUT 2 clk
Device-Specific Information: e:\cpld\fenpinqi\test.rpt
test
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 4 clr
Device-Specific Information: e:\cpld\fenpinqi\test.rpt
test
** EQUATIONS **
clk : INPUT;
clr : INPUT;
key : INPUT;
-- Node name is 'data0'
-- Equation name is 'data0', type is output
data0 = _LC3_F20;
-- Node name is 'data1'
-- Equation name is 'data1', type is output
data1 = _LC7_F20;
-- Node name is 'data2'
-- Equation name is 'data2', type is output
data2 = _LC4_F20;
-- Node name is 'data3'
-- Equation name is 'data3', type is output
data3 = _LC1_F20;
-- Node name is 'led0'
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