counter.vhd

基于FPGA的分频器设计,已经通过了仿真(VHDL语言编写)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter is
port (key,clr,clk:in std_logic;
	  output:out std_logic_vector(3 downto 0);
	  led:buffer std_logic_vector(6 downto 0));
end counter;
architecture behav of counter is
	signal bcd1n:std_logic_vector(3 downto 0):="0000";
	signal n: std_logic_vector(1 downto 0):="00";
	--signal m: std_logic:='0';
begin
process(clk,n,key)
begin
	if(clk'event and clk='0') then
		if(n="11") then
			n<="00";
		else
			n<=n+'1';
		end if;
	end if;
 	if(clr='0') then
   		bcd1n<="0000";
  	else 
		if(key'event and key='0') then		
			if(n="11") then
	  			if(bcd1n="1111") then
    	      		bcd1n<="0000";
        		else
         			bcd1n<=bcd1n+1;
				end if;
     		end if;
		end if;
	end if;
	output<=bcd1n;
end process;
process
begin
	case bcd1n is
		when "0000"=>led<="0111111";--0
		when "0001"=>led<="0000110";--1
		when "0010"=>led<="1011011";--2
		when "0011"=>led<="1001111";--3
		when "0100"=>led<="1100110";--4
		when "0101"=>led<="1101101";--5
		when "0110"=>led<="1111101";--6
		when "0111"=>led<="0000111";--7
		when "1000"=>led<="1111111";--8
		when "1001"=>led<="1101111";--9
		when "1010"=>led<="0111111";--10
		when "1011"=>led<="0111111";--
		when "1100"=>led<="0111111";
		when "1101"=>led<="0111111";
		when "1110"=>led<="0111111";
		when "1111"=>led<="0111111";
		when others=>led<="000001";
	end case;
end process;
end behav;