fenpinqi.vhd

基于FPGA的分频器设计,已经通过了仿真(VHDL语言编写)

--odd frequency division

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity fenpinqi is
	--GENERIC (N:integer);
port (clk:in std_logic;
	  key:in std_logic_vector(3 downto 0);
	  --en:in BIT;
	  --led:buffer std_logic_vector(6 downto 0);
	  outclk:out std_logic);
end fenpinqi;

architecture rtl of fenpinqi is
signal count1,count2:integer;
signal q,outclk1,outclk2:std_logic;
signal N: integer;
begin
q<=outclk1 and outclk2;

outclk<=q xor outclk1;

process
begin
case key is
	when "0000"=>N<=0;
	when "0001"=>N<=2;
	when "0010"=>N<=4;
	when "0011"=>N<=8;
	when "0100"=>N<=16;
	when "0101"=>N<=32;
	when "0110"=>N<=64;
	when "0111"=>N<=128;
	when "1000"=>N<=256;
	when "1001"=>N<=512;
	when "1010"=>N<=1024;
	when "1011"=>N<=2048;
	when "1100"=>N<=4096;
	when "1101"=>N<=8192;
	when "1111"=>N<=16384;
	when others=>n<=0;
end case;
end process;
process(clk)
begin
	if(clk'event and clk='1') then
	if(count1=N-1)then
	count1<=0;
	else
				count1<=count1+1;
		if count1<(integer(N/2)) then
			outclk1<='0';
		else
			outclk1<='1';
		end if;
	end if;
	end if;
end process;
process(clk)
begin
	if(clk'event and clk='0') then
	if(count2=N-1)then
			count2<=0;
	else
			count2<=count2+1;
		if count2<(integer(N/2)) then
			outclk2<='1';
		else
			outclk2<='0';
		end if;
	end if;
	end if;
end process;
end rtl;