__projnav.log

来自「这是一个FPGA的实验源码」· LOG 代码 · 共 1,753 行 · 第 1/5 页

   Number of SLICEs                  105 out of 1200    8%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9898d7) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
......................................
Phase 5.8 (Checksum:9a5ef1) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file song.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 700 unrouted;       REAL time: 0 secs 

Phase 2: 635 unrouted;       REAL time: 4 secs 

Phase 3: 187 unrouted;       REAL time: 4 secs 

Phase 4: 0 unrouted;       REAL time: 4 secs 

Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 4 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   22   |  0.069     |  0.486      |
+----------------------------+----------+--------+------------+-------------+
|           clk_4Hz          |   Local  |   27   |  1.211     |  3.050      |
+----------------------------+----------+--------+------------+-------------+
|             carry          |   Local  |   17   |  0.166     |  2.755      |
+----------------------------+----------+--------+------------+-------------+
|          clk_6MHz          |   Local  |    8   |  0.138     |  3.036      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 5 secs 
Total CPU time to PAR completion: 4 secs 

Peak Memory Usage:  54 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file song.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Fri Jan 13 09:15:40 2006
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module song . . .
PAR command line: par -w -intstyle ise -ol std -t 1 song_map.ncd song.ncd song.pcf
PAR completed successfully




Started process "Generate Programming File".

WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net carry is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "song.v"
Module <song> compiled
No errors in compilation
Analysis of file <song.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <song>.
Module <song> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <song>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================
INFO:Xst:1304 - Contents of register <high> in unit <song> never changes during circuit operation. The register is replaced by logic.

Synthesizing Unit <song>.
    Related source file is song.v.
WARNING:Xst:1780 - Signal <show_note> is never used or assigned.
WARNING:Xst:1780 - Signal <seg_select> is never used or assigned.
    Found 64x8-bit ROM for signal <$n0019>.
    Found 1-bit register for signal <speaker>.
    Found 8-bit comparator greatequal for signal <$n0008> created at line 21.
    Found 32-bit comparator greatequal for signal <$n0009> created at line 32.
    Found 8-bit adder for signal <$n0011> created at line 102.
    Found 8-bit comparator greatequal for signal <$n0012> created at line 101.
    Found 8-bit comparator greatequal for signal <$n0013> created at line 177.
    Found 1-bit register for signal <clk_4Hz>.
    Found 1-bit register for signal <clk_6MHz>.
    Found 8-bit up counter for signal <counter1>.
    Found 8-bit register for signal <counter2>.
    Found 32-bit up counter for signal <counter3>.
    Found 14-bit up counter for signal <divider>.
    Found 4-bit register for signal <high>.
    Found 4-bit register for signal <low>.
    Found 4-bit register for signal <med>.
    Found 14-bit register for signal <origin>.
    Summary:
	inferred   1 ROM(s).
	inferred   3 Counter(s).
	inferred  53 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   4 Comparator(s).
Unit <song> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 64x8-bit ROM                      : 1
# Adders/Subtractors               : 1
 8-bit adder                       : 1
# Counters                         : 3
 14-bit up counter                 : 1
 32-bit up counter                 : 1
 8-bit up counter                  : 1
# Registers                        : 11
 14-bit register                   : 1
 8-bit register                    : 2
 1-bit register                    : 3
 4-bit register                    : 5
# Comparators                      : 4
 8-bit comparator greatequal       : 3
 32-bit comparator greatequal      : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <low_ren_3> (without init value) is constant in block <song>.
WARNING:Xst:1710 - FF/Latch  <high_3> (without init value) is constant in block <song>.
WARNING:Xst:1710 - FF/Latch  <med_ren_3> (without init value) is constant in block <song>.
WARNING:Xst:1710 - FF/Latch  <high_1> (without init value) is constant in block <song>.
WARNING:Xst:1710 - FF/Latch  <high_2> (without init value) is constant in block <song>.
WARNING:Xst:1710 - FF/Latch  <low_3> (without init value) is constant in block <song>.
WARNING:Xst:1710 - FF/Latch  <med_3> (without init value) is constant in block <song>.

ERROR:Xst:528 - Multi-source in Unit <song> on signal <counter2<7>>
Sources are: 
   Output signal of FD instance <counter2_ren_7>
   Output signal of FD instance <counter2_7>

ERROR:Xst:528 - Multi-source in Unit <song> on signal <counter2<6>>
Sources are: 
   Output signal of FD instance <counter2_ren_6>
   Output signal of FD instance <counter2_6>

ERROR:Xst:528 - Multi-source in Unit <song> on signal <counter2<5>>
Sources are: 
   Output signal of FD instance <counter2_ren_5>
   Output signal of FD instance <counter2_5>

ERROR:Xst:528 - Multi-source in Unit <song> on signal <counter2<4>>
Sources are: 
   Output signal of FD instance <counter2_ren_4>
   Output signal of FD instance <counter2_4>

ERROR:Xst:528 - Multi-source in Unit <song> on signal <counter2<3>>
Sources are: 
   Output signal of FD instance <counter2_ren_3>
   Output signal of FD instance <counter2_3>

ERROR:Xst:528 - Multi-source in Unit <song> on signal <counter2<1>>
Sources are: 
   Output signal of FD instance <counter2_ren_1>
   Output signal of FD instance <counter2_1>

ERROR:Xst:528 - Multi-source in Unit <song> on signal <med<2>>
Sources are: 
   Output signal of FD instance <med_ren_2>
   Output signal of FD instance <med_2>

ERROR:Xst:528 - Multi-source in Unit <song> on signal <med<1>>
Sources are: 
   Output signal of FD instance <med_ren_1>
   Output signal of FD instance <med_1>

ERROR:Xst:528 - Multi-source in Unit <song> on signal <med<0>>
Sources are: 
   Output signal of FD instance <med_ren_0>
   Output signal of FD instance <med_0>

ERROR:Xst:528 - Multi-source in Unit <song> on signal <low<3>>
Sources are: 
   Signal <high<2>> in Unit <song> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <song> on signal <counter2<0>>
Sources are: 
   Output signal of FD instance <counter2_ren_0>
   Output signal of FD instance <counter2_0>

ERROR:Xst:528 - Multi-source in Unit <song> on signal <high<0>>
Sources are: 
   Output signal of FD instance <high_0>
   Signal <high<0>> in Unit <song> is assigned to GND

ERROR:Xst:528 - Multi-source in Unit <song> on signal <counter2<2>>
Sources are: 
   Output signal of FD instance <counter2_ren_2>
   Output signal of FD instance <counter2_2>

ERROR:Xst:528 - Multi-source in Unit <song> on signal <low<0>>
Sources are: 
   Output signal of FD instance <low_ren_0>
   Output signal of FD instance <low_0>

ERROR:Xst:528 - Multi-source in Unit <song> on signal <low<2>>
Sources are: 
   Output signal of FD instance <low_ren_2>
   Output signal of FD instance <low_2>

ERROR:Xst:528 - Multi-source in Unit <song> on signal <low<1>>
Sources are: 
   Output signal of FD instance <low_ren_1>
   Output signal of FD instance <low_1>
ERROR:Xst:415 - Synthesis failed
CPU : 2.32 / 3.24 s | Elapsed : 2.00 / 3.00 s
 
--> 

Total memory usage is 55680 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "song.v"
Module <song> compiled
No errors in compilation
Analysis of file <song.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <song>.
Module <song> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <song>.

=========================================================================
*                           HDL Synthesis                               *
=================================================================