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ERROR:HDLCompilers:26 - song.v line 257 expecting ';', found ':'ERROR:HDLCompilers:26 - song.v line 257 unexpected token: '='ERROR:HDLCompilers:26 - song.v line 259 unexpected token: '79'ERROR:HDLCompilers:26 - song.v line 259 expecting ';', found ':'ERROR:HDLCompilers:26 - song.v line 259 unexpected token: '='ERROR:HDLCompilers:26 - song.v line 261 unexpected token: '81'ERROR:HDLCompilers:26 - song.v line 261 expecting ';', found ':'ERROR:HDLCompilers:26 - song.v line 261 unexpected token: '='ERROR:HDLCompilers:26 - song.v line 263 unexpected token: '83'ERROR:HDLCompilers:26 - song.v line 263 expecting ';', found ':'ERROR:HDLCompilers:26 - song.v line 263 unexpected token: '='ERROR:HDLCompilers:26 - song.v line 265 unexpected token: '85'ERROR:HDLCompilers:26 - song.v line 265 expecting ';', found ':'ERROR:HDLCompilers:26 - song.v line 265 unexpected token: '='ERROR:HDLCompilers:26 - song.v line 267 unexpected token: '87'ERROR:HDLCompilers:26 - song.v line 267 expecting ';', found ':'ERROR:HDLCompilers:26 - song.v line 267 unexpected token: '='ERROR:HDLCompilers:26 - song.v line 269 unexpected token: '89'ERROR:HDLCompilers:26 - song.v line 269 expecting ';', found ':'ERROR:HDLCompilers:26 - song.v line 269 unexpected token: '='ERROR:HDLCompilers:26 - song.v line 271 unexpected token: '91'ERROR:HDLCompilers:26 - song.v line 271 expecting ';', found ':'ERROR:HDLCompilers:26 - song.v line 271 unexpected token: '='ERROR:HDLCompilers:26 - song.v line 273 unexpected token: '93'ERROR:HDLCompilers:26 - song.v line 273 expecting ';', found ':'ERROR:HDLCompilers:26 - song.v line 273 unexpected token: '='ERROR:HDLCompilers:26 - song.v line 275 unexpected token: '95'ERROR:HDLCompilers:26 - song.v line 275 expecting ';', found ':'ERROR:HDLCompilers:26 - song.v line 275 unexpected token: '='ERROR:HDLCompilers:26 - song.v line 277 unexpected token: '97'ERROR:HDLCompilers:26 - song.v line 277 expecting ';', found ':'ERROR:HDLCompilers:26 - song.v line 277 unexpected token: '='ERROR:HDLCompilers:26 - song.v line 279 unexpected token: 'endcase'ERROR:HDLCompilers:26 - song.v line 283 expecting ';', found 'EOF'ERROR:HDLCompilers:26 - song.v line 283 expecting 'endcase', found 'EOF'ERROR:HDLCompilers:26 - song.v line 283 expecting 'end', found 'EOF'Module <song> compiledERROR:HDLCompilers:26 - song.v line 283 expecting 'endmodule', found 'EOF'Analysis of file <song.prj> failed.--> Total memory usage is 48512 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "song.v"Module <song> compiledNo errors in compilationAnalysis of file <song.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <song>.Module <song> is correct for synthesis. Set property "resynthesize = true" for unit <song>.=========================================================================* HDL Synthesis *=========================================================================INFO:Xst:1304 - Contents of register <high> in unit <song> never changes during circuit operation. The register is replaced by logic.Synthesizing Unit <song>. Related source file is song.v.WARNING:Xst:1780 - Signal <show_note> is never used or assigned.WARNING:Xst:1780 - Signal <seg_select> is never used or assigned. Found 1-bit register for signal <speaker>. Found 8-bit comparator greatequal for signal <$n0005> created at line 21. Found 32-bit comparator greatequal for signal <$n0006> created at line 32. Found 8-bit comparator greatequal for signal <$n0008> created at line 177. Found 8-bit adder for signal <$n0011> created at line 178. Found 1-bit register for signal <clk_4Hz>. Found 1-bit register for signal <clk_6MHz>. Found 8-bit up counter for signal <counter1>. Found 8-bit register for signal <counter2>. Found 32-bit up counter for signal <counter3>. Found 14-bit up counter for signal <divider>. Found 4-bit register for signal <low>. Found 4-bit register for signal <med>. Found 14-bit register for signal <origin>. Summary: inferred 3 Counter(s). inferred 33 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 3 Comparator(s).Unit <song> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Adders/Subtractors : 1 8-bit adder : 1# Counters : 3 14-bit up counter : 1 32-bit up counter : 1 8-bit up counter : 1# Registers : 7 14-bit register : 1 8-bit register : 1 1-bit register : 3 4-bit register : 2# Comparators : 3 8-bit comparator greatequal : 2 32-bit comparator greatequal : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================WARNING:Xst:1710 - FF/Latch <med_3> (without init value) is constant in block <song>.WARNING:Xst:1710 - FF/Latch <low_3> (without init value) is constant in block <song>.Optimizing unit <song> ...Loading device for application Xst from file 'v100.nph' in environment D:/Program/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block song, actual ratio is 10.FlipFlop speaker has been replicated 1 time(s) to handle iob=true attribute.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s100tq144-6 Number of Slices: 133 out of 1200 11% Number of Slice Flip Flops: 86 out of 2400 3% Number of 4 input LUTs: 232 out of 2400 9% Number of bonded IOBs: 1 out of 96 1% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk_4Hz:Q | NONE | 28 |clk_6MHz:Q | NONE | 14 |carry(carry30:O) | NONE(*)(speaker_1) | 2 |clk | BUFGP | 42 |-----------------------------------+------------------------+-------+(*) This 1 clock signal(s) are generated by combinatorial logic,and XST is not able to identify which are the primary clock signals.Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.Timing Summary:---------------Speed Grade: -6 Minimum period: 14.499ns (Maximum Frequency: 68.970MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 6.788ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd d:\program\xilinx\bin\yx/_ngo -ucsong.ucf -p xc2s100-tq144-6 song.ngc song.ngd Reading NGO file "d:/program/xilinx/bin/yx/song.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "song.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 41284 kilobytesWriting NGD file "song.ngd" ...Writing NGDBUILD log file "song.bld"...NGDBUILD done.Completed process "Translate".
Started process "Map".Using target part "2s100tq144-6".Removing unused or disabled logic...Running cover...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary:Number of errors: 0Number of warnings: 1Logic Utilization: Number of Slice Flip Flops: 85 out of 2,400 3% Number of 4 input LUTs: 182 out of 2,400 7%Logic Distribution: Number of occupied Slices: 126 out of 1,200 10% Number of Slices containing only related logic: 126 out of 126 100% Number of Slices containing unrelated logic: 0 out of 126 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 234 out of 2,400 9% Number used as logic: 182 Number used as a route-thru: 52 Number of bonded IOBs: 1 out of 92 1% IOB Flip Flops: 1 Number of GCLKs: 1 out of 4 25% Number of GCLKIOBs: 1 out of 4 25%Total equivalent gate count for design: 2,197Additional JTAG gate count for IOBs: 96Peak Memory Usage: 61 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Mapping completed.See MAP report file "song_map.mrp" for details.Completed process "Map".Mapping Module song . . .
MAP command line:
map -intstyle ise -p xc2s100-tq144-6 -cm area -pr b -k 4 -c 100 -tx off -o song_map.ncd song.ngd song.pcf
Mapping Module song: DONE
Started process "Place & Route".Constraints file: song.pcfLoading device database for application Par from file "song_map.ncd". "song" is an NCD, version 2.38, device xc2s100, package tq144, speed -6Loading device for application Par from file 'v100.nph' in environmentD:/Program/Xilinx.Device speed data version: PRODUCTION 1.27 2004-06-25.Resolving physical constraints.Finished resolving physical constraints.Device utilization summary: Number of External GCLKIOBs 1 out of 4 25% Number of External IOBs 1 out of 92 1% Number of LOCed External IOBs 1 out of 1 100% Number of SLICEs 126 out of 1200 10% Number of GCLKs 1 out of 4 25%Overall effort level (-ol): Standard (set by user)Placer effort level (-pl): Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl): Standard (set by user)Phase 1.1Phase 1.1 (Checksum:98997f) REAL time: 0 secs Phase 2.23Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs Phase 3.3Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8............................................Phase 5.8 (Checksum:9aa799) REAL time: 0 secs Phase 6.5Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file song.ncd.Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs ⌨️ 快捷键说明
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