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这是一个FPGA的实验源码

# Reading D:/Program Files/win32/../tcl/vsim/pref.tcl 
# //  ModelSim SE 6.0 Aug 19 2004 
# //
# //  Copyright Mentor Graphics Corporation 2004
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# do song.ldo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vlog 6.0 Compiler 2004.08 Aug 19 2004
# -- Compiling module song
# 
# Top level modules:
# 	song
# Model Technology ModelSim SE vlog 6.0 Compiler 2004.08 Aug 19 2004
# -- Compiling module glbl
# 
# Top level modules:
# 	glbl
# vsim -L xilinxcorelib_ver -L unisims_ver -t 1ps +maxdelays song glbl 
# Loading work.song
# Loading work.glbl
# ** Warning: (vsim-3010) [TSCALE] - Module 'glbl' has a `timescale directive in effect, but previous modules do not.
#         Region: /glbl
# .wave
# .main_pane.workspace
# .main_pane.signals.interior.cs