song.syr

这是一个FPGA的实验源码

#      LUT4                        : 8
#      LUT4_D                      : 1
#      LUT4_L                      : 5
#      MUXCY                       : 64
#      VCC                         : 1
#      XORCY                       : 52
# FlipFlops/Latches                : 86
#      FD                          : 4
#      FDE                         : 18
#      FDR                         : 50
#      FDS                         : 14
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 14
#      IBUF                        : 3
#      OBUF                        : 11
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100tq144-6 

 Number of Slices:                      81  out of   1200     6%  
 Number of Slice Flip Flops:            86  out of   2400     3%  
 Number of 4 input LUTs:                97  out of   2400     4%  
 Number of bonded IOBs:                 14  out of     96    14%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_4Hz:Q                          | NONE                   | 16    |
clk                                | BUFGP                  | 48    |
clk_6MHz:Q                         | NONE                   | 20    |
carry(carry30:O)                   | NONE(*)(speaker_1)     | 2     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.785ns (Maximum Frequency: 102.197MHz)
   Minimum input arrival time before clock: 4.749ns
   Maximum output required time after clock: 6.788ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk_4Hz:Q'
Delay:               6.895ns (Levels of Logic = 1)
  Source:            med_0 (FF)
  Destination:       origin_6 (FF)
  Source Clock:      clk_4Hz:Q rising
  Destination Clock: clk_4Hz:Q rising

  Data Path: med_0 to origin_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q             27   1.085   3.195  med_0 (med_0)
     LUT3:I0->O            3   0.549   1.332  Ker28061 (N2808)
     FDS:S                     0.734          origin_8
    ----------------------------------------
    Total                      6.895ns (2.368ns logic, 4.527ns route)
                                       (34.3% logic, 65.7% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               9.744ns (Levels of Logic = 14)
  Source:            counter3_5 (FF)
  Destination:       clk_4Hz (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: counter3_5 to clk_4Hz
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   1.085   1.206  counter3_5 (counter3_5)
     LUT1_L:I0->LO         1   0.549   0.000  counter3<5>_rt (counter3<5>_rt)
     MUXCY:S->O            1   0.659   0.000  Andcy (And_cyo)
     MUXCY:CI->O           1   0.042   0.000  norcy (nor_cyo)
     MUXCY:CI->O           1   0.042   0.000  Andcy_rn_0 (And_cyo1)
     MUXCY:CI->O           1   0.042   0.000  norcy_rn_0 (nor_cyo1)
     MUXCY:CI->O           1   0.042   0.000  Andcy_rn_1 (And_cyo2)
     MUXCY:CI->O           1   0.042   0.000  norcy_rn_1 (nor_cyo2)
     MUXCY:CI->O           1   0.042   0.000  Andcy_rn_2 (And_cyo3)
     MUXCY:CI->O           1   0.042   0.000  Andcy_rn_3 (And_cyo4)
     MUXCY:CI->O           1   0.042   0.000  norcy_rn_2 (nor_cyo3)
     MUXCY:CI->O           1   0.042   0.000  Andcy_rn_4 (And_cyo5)
     MUXCY:CI->O           1   0.042   0.000  norcy_rn_3 (nor_cyo4)
     MUXCY:CI->O          33   0.042   3.465  norcy_rn_4 (_n0013)
     LUT1:I0->O            1   0.549   1.035  _n00821 (_n0082)
     FDR:R                     0.734          clk_4Hz
    ----------------------------------------
    Total                      9.744ns (4.038ns logic, 5.706ns route)
                                       (41.4% logic, 58.6% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk_6MHz:Q'
Delay:               9.785ns (Levels of Logic = 17)
  Source:            divider_8 (FF)
  Destination:       divider_13 (FF)
  Source Clock:      clk_6MHz:Q rising
  Destination Clock: clk_6MHz:Q rising

  Data Path: divider_8 to divider_13
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   1.085   1.206  divider_8 (divider_8)
     LUT2:I0->O            1   0.549   1.035  carry0 (CHOICE14)
     LUT4_D:I0->O         16   0.549   2.520  carry30 (carry)
     LUT3_L:I0->LO         1   0.549   0.000  divider_inst_lut3_01 (divider_inst_lut3_0)
     MUXCY:S->O            1   0.659   0.000  divider_inst_cy_1 (divider_inst_cy_1)
     MUXCY:CI->O           1   0.042   0.000  divider_inst_cy_2 (divider_inst_cy_2)
     MUXCY:CI->O           1   0.042   0.000  divider_inst_cy_3 (divider_inst_cy_3)
     MUXCY:CI->O           1   0.042   0.000  divider_inst_cy_4 (divider_inst_cy_4)
     MUXCY:CI->O           1   0.042   0.000  divider_inst_cy_5 (divider_inst_cy_5)
     MUXCY:CI->O           1   0.042   0.000  divider_inst_cy_6 (divider_inst_cy_6)
     MUXCY:CI->O           1   0.042   0.000  divider_inst_cy_7 (divider_inst_cy_7)
     MUXCY:CI->O           1   0.042   0.000  divider_inst_cy_8 (divider_inst_cy_8)
     MUXCY:CI->O           1   0.042   0.000  divider_inst_cy_9 (divider_inst_cy_9)
     MUXCY:CI->O           1   0.042   0.000  divider_inst_cy_10 (divider_inst_cy_10)
     MUXCY:CI->O           1   0.042   0.000  divider_inst_cy_11 (divider_inst_cy_11)
     MUXCY:CI->O           1   0.042   0.000  divider_inst_cy_12 (divider_inst_cy_12)
     MUXCY:CI->O           0   0.042   0.000  divider_inst_cy_13 (divider_inst_cy_13)
     XORCY:CI->O           1   0.420   0.000  divider_inst_sum_13 (divider_inst_sum_13)
     FDE:D                     0.709          divider_13
    ----------------------------------------
    Total                      9.785ns (5.024ns logic, 4.761ns route)
                                       (51.3% logic, 48.7% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'carry30:O'
Delay:               3.025ns (Levels of Logic = 0)
  Source:            speaker (FF)
  Destination:       speaker (FF)
  Source Clock:      carry30:O rising
  Destination Clock: carry30:O rising

  Data Path: speaker to speaker
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   1.085   1.206  speaker (speaker_OBUF)
     FDR:R                     0.734          speaker
    ----------------------------------------
    Total                      3.025ns (1.819ns logic, 1.206ns route)
                                       (60.1% logic, 39.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk_6MHz:Q'
Offset:              4.749ns (Levels of Logic = 2)
  Source:            index<1> (PAD)
  Destination:       song2_enable (FF)
  Destination Clock: clk_6MHz:Q rising

  Data Path: index<1> to song2_enable
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             3   0.776   1.332  index_1_IBUF (index_1_IBUF)
     LUT3:I0->O            2   0.549   1.206  _n00851 (_n0085)
     FDE:CE                    0.886          song1_enable
    ----------------------------------------
    Total                      4.749ns (2.211ns logic, 2.538ns route)
                                       (46.6% logic, 53.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'carry30:O'
Offset:              6.788ns (Levels of Logic = 1)
  Source:            speaker_1 (FF)
  Destination:       speaker (PAD)
  Source Clock:      carry30:O rising

  Data Path: speaker_1 to speaker
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   1.085   1.035  speaker_1 (speaker_1)
     OBUF:I->O                 4.668          speaker_OBUF (speaker)
    ----------------------------------------
    Total                      6.788ns (5.753ns logic, 1.035ns route)
                                       (84.8% logic, 15.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_6MHz:Q'
Offset:              6.788ns (Levels of Logic = 1)
  Source:            seg_scan_1_1 (FF)
  Destination:       seg_scan<1> (PAD)
  Source Clock:      clk_6MHz:Q rising

  Data Path: seg_scan_1_1 to seg_scan<1>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   1.085   1.035  seg_scan_1_1 (seg_scan_1_1)
     OBUF:I->O                 4.668          seg_scan_1_OBUF (seg_scan<1>)
    ----------------------------------------
    Total                      6.788ns (5.753ns logic, 1.035ns route)
                                       (84.8% logic, 15.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              6.788ns (Levels of Logic = 1)
  Source:            seg_4_1 (FF)
  Destination:       seg<6> (PAD)
  Source Clock:      clk rising

  Data Path: seg_4_1 to seg<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   1.085   1.035  seg_4_1 (seg_4_1)
     OBUF:I->O                 4.668          seg_6_OBUF (seg<6>)
    ----------------------------------------
    Total                      6.788ns (5.753ns logic, 1.035ns route)
                                       (84.8% logic, 15.2% route)

=========================================================================
CPU : 3.88 / 5.99 s | Elapsed : 4.00 / 6.00 s
 
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Total memory usage is 59144 kilobytes