song.syr

这是一个FPGA的实验源码

Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 1.60 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 1.60 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: song.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : song.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : song
Output Format                      : NGC
Target Device                      : xc2s100-6-tq144

---- Source Options
Top Module Name                    : song
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : song.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "song.v"
Module <song> compiled
No errors in compilation
Analysis of file <song.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <song>.
Module <song> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <song>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================
INFO:Xst:1304 - Contents of register <counter2> in unit <song> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <counter4> in unit <song> never changes during circuit operation. The register is replaced by logic.

Synthesizing Unit <song>.
    Related source file is song.v.
    Using one-hot encoding for signal <$old_counter4_4>.
    Using one-hot encoding for signal <$old_counter2_3>.
    Found 1-bit register for signal <speaker>.
    Found 3-bit register for signal <seg_scan>.
    Found 7-bit register for signal <seg>.
    Found 8-bit comparator greatequal for signal <$n0012> created at line 30.
    Found 32-bit comparator greatequal for signal <$n0013> created at line 42.
    Found 1-bit adder for signal <$old_seg_select_2>.
    Found 1-bit register for signal <clk_4Hz>.
    Found 1-bit register for signal <clk_6MHz>.
    Found 8-bit up counter for signal <counter1>.
    Found 64-bit register for signal <counter2>.
    Found 32-bit up counter for signal <counter3>.
    Found 128-bit register for signal <counter4>.
    Found 14-bit up counter for signal <divider>.
    Found 4-bit register for signal <high>.
    Found 4-bit register for signal <low>.
    Found 4-bit register for signal <med>.
    Found 14-bit register for signal <origin>.
    Found 1-bit register for signal <seg_select>.
    Found 4-bit register for signal <show_note>.
    Found 1-bit register for signal <song1_enable>.
    Found 1-bit register for signal <song2_enable>.
    Summary:
	inferred   3 Counter(s).
	inferred 238 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   2 Comparator(s).
Unit <song> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 1-bit adder                       : 1
# Counters                         : 3
 14-bit up counter                 : 1
 32-bit up counter                 : 1
 8-bit up counter                  : 1
# Registers                        : 13
 7-bit register                    : 1
 3-bit register                    : 1
 14-bit register                   : 1
 4-bit register                    : 4
 1-bit register                    : 6
# Comparators                      : 2
 32-bit comparator greatequal      : 1
 8-bit comparator greatequal       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <med_3> (without init value) is constant in block <song>.
WARNING:Xst:1710 - FF/Latch  <high_3> (without init value) is constant in block <song>.
WARNING:Xst:1710 - FF/Latch  <low_3> (without init value) is constant in block <song>.
WARNING:Xst:1710 - FF/Latch  <show_note_3> (without init value) is constant in block <song>.
WARNING:Xst:1710 - FF/Latch  <seg_scan_2> (without init value) is constant in block <song>.
WARNING:Xst:1710 - FF/Latch  <low_2> (without init value) is constant in block <song>.
WARNING:Xst:1710 - FF/Latch  <med_2> (without init value) is constant in block <song>.
WARNING:Xst:1710 - FF/Latch  <high_0> (without init value) is constant in block <song>.
WARNING:Xst:1710 - FF/Latch  <high_1> (without init value) is constant in block <song>.
WARNING:Xst:1710 - FF/Latch  <high_2> (without init value) is constant in block <song>.
WARNING:Xst:1710 - FF/Latch  <show_note_2> (without init value) is constant in block <song>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <seg_5> (without init value) is constant in block <song>.

Optimizing unit <song> ...
Loading device for application Xst from file 'v100.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Register seg_6 equivalent to seg_3 has been removed
Register seg_select equivalent to seg_scan_1 has been removed
Register med_1 equivalent to med_0 has been removed
Register low_1 equivalent to low_0 has been removed
Register show_note_1 equivalent to show_note_0 has been removed
Register seg_3 equivalent to seg_4 has been removed
Found area constraint ratio of 100 (+ 5) on block song, actual ratio is 5.
FlipFlop speaker has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop seg_scan_1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop seg_4 has been replicated 2 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : song.ngr
Top Level Output File Name         : song
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 15

Macro Statistics :
# Registers                        : 15
#      1-bit register              : 6
#      14-bit register             : 1
#      3-bit register              : 1
#      4-bit register              : 4
#      7-bit register              : 1
#      8-bit register              : 2
# Counters                         : 1
#      14-bit up counter           : 1
# Adders/Subtractors               : 2
#      8-bit adder                 : 2
# Comparators                      : 2
#      32-bit comparator greatequal: 1
#      8-bit comparator greatequal : 1

Cell Usage :
# BELS                             : 215
#      GND                         : 1
#      LUT1                        : 43
#      LUT1_L                      : 7
#      LUT2                        : 7
#      LUT3                        : 10
#      LUT3_D                      : 2
#      LUT3_L                      : 14