_info

Sdr SDRAM控制器参考设计,很好的

m255
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dD:\Projects\altera\lpcores\ddr\release\V1_1\simulation
valtclklock
IQe[@Sne^mL9YOa39Ad<V43
w958849419
Faltclklock.v
OP;L;5.3d;15
V^dCdJn^KETZYi;YL:Rz<K0
31
o-work work
vddr_command
I?WYzLZhS7PBk5keRhdjbn0
w958849624
FD:/Projects/altera/lpcores/ddr/release/V1_1/simulation/ddr_compile_all.v
Fddr_command.v
Fparams.v
OP;L;5.3d;15
V2gXBideVWTYaS0D<n]dF51
31
o-work work
vddr_control_interface
IT[L4B]BdmjY]TSc<6CGI:2
w958976278
Fddr_control_interface.v
Fparams.v
OP;L;5.3d;15
VkN6ANAj<9dKNE@?[;]Sjk1
31
o-work work
vddr_data_path
I]OR5>L;UCbkLC?ElKoSEc3
w958966616
Fddr_data_path.v
Fparams.v
OP;L;5.3d;15
VGbXJ`X[7hh7=VC:3Nf2h03
31
o-work work
vddr_sdram
IH@6?A;TRT9l?NJR=V@QHe3
w958967849
Fddr_sdram.v
Fparams.v
OP;L;5.3d;15
VoK;lTId`lN7L0S]FoTR=i0
31
o-work work
vddr_sdram_tb
I4e`=AQMAHO1;B;W@P>c3K2
w958784290
Fddr_sdram_tb.v
Fparams.v
OP;L;5.3d;15
VVo=E@^HMLo:^jdE0N4jE:2
31
o-work work
vmt46v4m16
IG8CWQZYCV6o3lMk7cBEa30
w954394608
Fmt46v4m16.v
OP;L;5.3d;15
VDaXH;OfzI[az`g`OD?UAR0
31
o-work work
vpll1
I[QDZeLNk]:NzU@mJ;hA?03
w958849358
Fpll1.v
OP;L;5.3d;15
V@CH?[_eACOd?oN=?KAoSa3
31
o-work work