ddr_sdram.psf

Sdr SDRAM控制器参考设计,很好的

DEFAULT_PARAMETERS
{
	~ELA~WIDTH = 0;
	~ELA~DEPTH = 0;
}
SYNTHESIS_FITTING_SETTINGS
{
	AUTO_TURBO_BIT = ON;
	AUTO_OPEN_DRAIN_PINS = ON;
	AUTO_PARALLEL_EXPANDERS = ON;
	AUTO_FAST_OUTPUT_REGISTERS = OFF;
	AUTO_FAST_INPUT_REGISTERS = OFF;
	AUTO_CASCADE_CHAINS = ON;
	AUTO_CARRY_CHAINS = ON;
	PARALLEL_EXPANDER_CHAIN_LENGTH = 16;
	CASCADE_CHAIN_LENGTH = 2;
	CARRY_CHAIN_LENGTH = 32;
	OPTIMIZATION_TECHNIQUE = SPEED;
	AUTO_IMPLEMENT_IN_ROM = OFF;
	AUTO_GLOBAL_MEMORY_CONTROLS = OFF;
	AUTO_GLOBAL_REGISTER_CONTROLS = ON;
	AUTO_GLOBAL_OE = ON;
	AUTO_GLOBAL_CLOCK = ON;
	TURBO_BIT = ON;
	IGNORE_SOFT_BUFFERS = ON;
	IGNORE_LCELL_BUFFERS = OFF;
	IGNORE_GLOBAL_BUFFERS = OFF;
	IGNORE_CASCADE_BUFFERS = OFF;
	IGNORE_CARRY_BUFFERS = OFF;
	PCI_IO = OFF;
	SLOW_SLEW_RATE = OFF;
	STATE_MACHINE_PROCESSING = AUTO;
	REMOVE_DUPLICATE_LOGIC = ON;
	REMOVE_DUPLICATE_REGISTERS = ON;
	PRESERVE_HIERARCHICAL_BOUNDARY = OFF;
	AUTO_PACKED_REGISTERS = OFF;
	ALLOW_XOR_GATE_USAGE = OFF;
	TECHNOLOGY_MAPPER = AUTO;
	NOT_GATE_PUSH_BACK = OFF;
}
DEFAULT_TIMING_REQUIREMENTS
{
	INCLUDE_PIN_DELAYS_IN_CALCULATIONS = OFF;
	CUT_OFF_IO_PIN_FEEDBACK = ON;
	CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
	CUT_OFF_READ_DURING_WRITE_PATHS = ON;
	CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON;
	IGNORE_CLOCK_SETTINGS = ON;
	SOURCES_PER_DESTINATION_INCLUDE_COUNT = 300;
	TCO_REQUIREMENT = 10ns;
}
PROJECT_INFO(ddr_sdram)
{
	USER_CONFIGURATION = "SINGLE-USER";
}
THIRD_PARTY_EDA_TOOLS(ddr_sdram)
{
	EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = SYNPLIFY;
	EDA_SIMULATION_TOOL = "<NONE>";
	EDA_TIMING_ANALYSIS_TOOL = "<NONE>";
}
EDA_TOOL_SETTINGS(eda_timing_analysis)
{
	EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
	EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
	EDA_FLATTEN_BUSES = ON;
	EDA_MAP_ILLEGAL_CHARACTERS = OFF;
	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
	EDA_OUTPUT_DATA_FORMAT = NONE;
}
EDA_TOOL_SETTINGS(eda_simulation)
{
	EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
	EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
	EDA_FLATTEN_BUSES = OFF;
	EDA_MAP_ILLEGAL_CHARACTERS = OFF;
	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
	EDA_OUTPUT_DATA_FORMAT = NONE;
}
EDA_TOOL_SETTINGS(eda_design_synthesis)
{
	EDA_INPUT_GND_NAME = GND;
	EDA_INPUT_VCC_NAME = VCC;
	EDA_LMF_FILE = synplcty.lmf;
	EDA_SHOW_LMF_MAPPING_MESSAGES = OFF;
	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
	EDA_INPUT_DATA_FORMAT = "VERILOG HDL";
	EDA_OUTPUT_DATA_FORMAT = EDIF;
}