mux4.vhd

用vhdl硬件语言设计的16位cpu

-- mux4.vhd

-- This module implements a 4-to-1 multiplexor for ALU

-- Inputs: 
--    A, B, C, D  - 16-bit mux inputs 
--    Sel         - 2-bit Select for mux 

-- Outputs: 
--    Z           - 16-bit mux output

-- Author:    Easyright
-- E-mail:    [e-mail]
-- Date:      17-08-2003
-- Copyright: http://www.EasyRight.net

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity mux4 is
  port (
    Sel:        in std_logic_vector(1 downto 0);
    A, B, C, D: in std_logic_vector(15 downto 0);
    Z:          out std_logic_vector(15 downto 0)
  );
end mux4;

architecture arc_mux4 of mux4 is
begin
  with Sel select 
    Z <= A when "00",
         B when "01", 
         C when "10", 
         D when "11", 
         A when others;
end arc_mux4;