sppinterf.vhd

Image_Filter_An_Image_halftone is performed over data loaded into the on board RAM and presented on

--based on the demo by
--Miguel A. Aguirre Echanove. University of Sevilla (SPAIN)
--Dpt. of Ingenieria Electronica. [e-mail]
--Modified by Jon Tombs [e-mail]

library IEEE;
use IEEE.std_logic_1164.all;

entity sppinterf is
    generic (ADDR_SIZE: integer := 2);
    port (
      clk: in STD_LOGIC;
      reset: out STD_LOGIC;
      P16: in STD_LOGIC;
	P44: in STD_LOGIC;
	P45: in STD_LOGIC;
	P46: in STD_LOGIC;
	P47: in STD_LOGIC;
	P48: in STD_LOGIC;
	P49: in STD_LOGIC;
	P70: out STD_LOGIC;
	P77: out STD_LOGIC;
	P66: out STD_LOGIC;
	P69: out STD_LOGIC;
      din: in STD_LOGIC_VECTOR(7 downto 0);
	dout: out STD_LOGIC_VECTOR(7 downto 0);
	addr: out STD_LOGIC_VECTOR(ADDR_SIZE-1 downto 0);
	read: out STD_LOGIC;
	write: out STD_LOGIC
    );
end sppinterf;

architecture sppinterf_arch of sppinterf is
component TDO port (O: in std_logic); end component;
component TDI port (I: out std_logic); end component;
--component TCK port (I: inout std_logic); end component;
component TMS port (I: out std_logic); end component;
component MD0 port (I: out std_logic); end component;
component MD1 port (O: in std_logic); end component;
component MD2 port (I: out std_logic); end component;
component IBUF port(I: in std_logic;O: out std_logic); end component;
component OBUF port(I: in std_logic;O: out std_logic); end component;
component IFD port (C,D: in std_logic; Q: out std_logic); end component;
--component STARTUP port (GSR: in std_logic);   end component;

component spp_RegSinc is
    generic(N: integer :=8);
    port (
        clk: in STD_LOGIC;
        reset: in STD_LOGIC;
        load: in STD_LOGIC; 
        din: in STD_LOGIC_VECTOR (N-1 downto 0);
        dout: out STD_LOGIC_VECTOR (N-1 downto 0)
    );
end component;
component spp_FFcleaner is
    port (
        D: in STD_LOGIC;
        CLK: in STD_LOGIC;
        RST: in STD_LOGIC;
        Q: out STD_LOGIC
    );
end component;
component spp_fsmrdwr is
port (
        clk: in STD_LOGIC;
        rst: in STD_LOGIC;
        wrexb: in STD_LOGIC;
        rdexb: in STD_LOGIC;
        wrint: out STD_LOGIC;
        aleint: out STD_LOGIC;
        rdint: out STD_LOGIC;
        nibble: out STD_LOGIC
    );
end component;

component spp_Muxsal is
    port (
        I0: in STD_LOGIC;
        I1: in STD_LOGIC;
        I2: in STD_LOGIC;
        I3: in STD_LOGIC;
        I4: in STD_LOGIC;
        I5: in STD_LOGIC;
        I6: in STD_LOGIC;
        I7: in STD_LOGIC;
        Nibble: in STD_LOGIC;
        datard: out STD_LOGIC_VECTOR (4 downto 0)
    );
end component;


signal writeb,wrint,readb,aleint,rdint,nibble : std_logic;
signal ddisp,data,dw1,dw0,dw2,dw3: STD_LOGIC_VECTOR (7 downto 0);
signal drd,daux : STD_LOGIC_VECTOR (4 downto 0);
signal pw,pr : STD_LOGIC_VECTOR (3 downto 0);
signal ad : STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);
signal Apinrst,rst,Apinwrextb,wrextb: std_logic; -- For XS40 v1.3 or older
signal rdextb,Apinrdextb: std_logic;
signal Apindaux4,Apindata6,Apindata7,A1,D1,G1: std_logic;


begin

--I use the special signals with this method
--sio0:  TCK port map (Apinrst);
sio1:  TMS port map (Apinrdextb); 
sio2:  TDI port map (Apinwrextb);
sio3:  TDO port map (Apindaux4);
sio4:  MD0 port map (Apindata6);
sio5:  MD2 port map (Apindata7);
--bsio0: IBUF port map(Apinrst,rst); -- For XS40 v1.3 or older 
--bstart: STARTUP port map(rst);
rst <= P16;
bsio1: IBUF port map(Apinrdextb,rdextb); 
bsio2: IBUF port map(Apinwrextb,wrextb); -- For XS40 v1.3 or older
bsio4: IBUF port map(Apindata6,data(6)); 
bsio5: IBUF port map(Apindata7,data(7)); 
bsio3: OBUF port map(daux(4),Apindaux4); 


reset <= rst;
P69 <= daux(3);
P66 <= daux(2);
P77 <= daux(1);
P70 <= daux(0); 
addr <= ad;
data(5 downto 0) <= P49 & P48 & P47 & P46 & P45 & P44;
dout <= data;
ddisp <= din;
write <= wrint;
read <= rdint;
fsm1: spp_fsmrdwr 
    port map(clk,rst,writeb,readb,wrint,aleint,rdint,nibble);

--Address Register
rega: spp_RegSinc 
    generic map(ADDR_SIZE)
    port map(clk,rst,aleint,data(ADDR_SIZE-1 downto 0),ad);
  
--Store reading Data in an output register
regr: spp_RegSinc 
    generic map(5)
    port map(clk,rst,rdint,drd,daux);

--This can be included in the input Pad
ffcln1: spp_FFcleaner 
    port map(wrextb,clk,rst,writeb);
ffcln2: spp_FFcleaner 
    port map(rdextb,clk,rst,readb);

--Multiplexer for Nibble selection
muxrd: spp_Muxsal
    port map(ddisp(0),ddisp(1),ddisp(2),ddisp(3),ddisp(4),
    ddisp(5),ddisp(6),ddisp(7),Nibble,drd);
end sppinterf_arch;
--Generic register...
--Miguel A. Aguirre Echanove. University of Sevilla (SPAIN)
--Dpt. of Ingenieria Electronica. [e-mail]
--

library IEEE;
use IEEE.std_logic_1164.all;

entity spp_RegSinc is
    generic(N: integer :=8);
    port (
        clk: in STD_LOGIC;
        reset: in STD_LOGIC;
        load: in STD_LOGIC; 
        din: in STD_LOGIC_VECTOR (N-1 downto 0);
        dout: out STD_LOGIC_VECTOR (N-1 downto 0)
    );
end spp_RegSinc;

architecture RegSinc_arch of spp_RegSinc is
signal aux,doutaux: STD_LOGIC_VECTOR (N-1 downto 0);
begin
process (din,doutaux,load)
begin
	   if(load='1') then
	   	aux<=din;
	   else
	   	aux<=doutaux;
	   end if;
end process;

process(clk,reset)
begin
	if(reset='1') then
	   for i in 0 to N-1 loop
	      doutaux(i)<='0';
	   end loop;
	 elsif(clk='1') and (clk'event) then
		doutaux<=aux;
	 end if;
end process;
dout<=doutaux; --It's not quite elegant, but Xilinx recommends it;
end RegSinc_arch;
--FF for glitch filtering
--Miguel A. Aguirre Echanove. University of Sevilla (SPAIN)
--Dpt. of Ingenieria Electronica. [e-mail]
--

library IEEE;
use IEEE.std_logic_1164.all;

entity spp_FFcleaner is
    port (
        D: in STD_LOGIC;
        CLK: in STD_LOGIC;
        RST: in STD_LOGIC;
        Q: out STD_LOGIC
    );
end spp_FFcleaner;

architecture FFcleaner_arch of spp_FFcleaner is
begin
process(CLK,RST)
begin
	if(RST='1') then
		Q<='0';
	elsif(CLK'event) and (CLK='1') then
		Q<=D;
	end if;
end process;
end FFcleaner_arch;
--Fsm For Access Protocol
--Miguel A. Aguirre Echanove. University of Sevilla (SPAIN)
--Dpt. of Ingenieria Electronica. [e-mail]
--
library IEEE;
use IEEE.std_logic_1164.all;

entity spp_fsmrdwr is
    port (
        clk: in STD_LOGIC;
        rst: in STD_LOGIC;
        wrexb: in STD_LOGIC;
        rdexb: in STD_LOGIC;
        wrint: out STD_LOGIC;
        aleint: out STD_LOGIC;
        rdint: out STD_LOGIC;
        nibble: out STD_LOGIC
    );
end spp_fsmrdwr;

architecture fsmrdwr_arch of spp_fsmrdwr is
type state is (reposo,espescr,escribe,espdir,capdir,esplee0,lee0,esplee1,lee1);
signal prestate,nextstate : state;
begin
fsm : process (wrexb,rdexb,prestate)
begin

case prestate is
	when reposo =>--estado de partida
		wrint<='0';rdint<='0';aleint<='0';nibble<='0';		
		if(wrexb='1')and(rdexb='1') then 
			nextstate <= reposo;
		elsif(wrexb='0')and(rdexb='1') then
			nextstate <= espescr;
		elsif(wrexb='0')and(rdexb='0') then
			nextstate <= espdir;
		else
			nextstate <= esplee0;
		end if;
	when espescr =>--esperar a dar la orden de escritura
		wrint<='0';rdint<='0';aleint<='0';nibble<='0';		
		if(wrexb='0')and(rdexb='1') then
			nextstate <= espescr;
		elsif(wrexb='0')and(rdexb='0') then
			nextstate <= espdir;
		else
			nextstate <= escribe;
		end if;
	when escribe =>--dar orden de escritura
		rdint<='0';aleint<='0';nibble<='0';		
		wrint <='1';
		if(wrexb='1')and(rdexb='1') then 
			nextstate <= reposo;
		else				
			nextstate <= escribe;
		end if;
	when espdir =>--esperar a capturar la direccion
		wrint<='0';rdint<='0';aleint<='0';nibble<='0';		
		if(wrexb='0')and(rdexb='0') then
			nextstate <= espdir;
		else
			nextstate <= capdir;
		end if;			
	when capdir =>--capturar direccion
		wrint<='0';rdint<='0';nibble<='0';		
		aleint<='1';
		if(wrexb='1')and(rdexb='1') then 
			nextstate <= reposo;
		else				
			nextstate <= capdir;
		end if;	
			
	when esplee0 =>--esperar a leer
		wrint<='0';rdint<='0';aleint<='0';nibble<='0';		
		if(wrexb='1')and(rdexb='0') then
			nextstate <= esplee0;
		elsif(wrexb='0')and(rdexb='0') then
			nextstate <= espdir;
		else
			nextstate <= lee0;
		end if;
	when lee0 =>--leer nibble menos significativo
		wrint<='0';aleint<='0';nibble<='0';		
		rdint<='1';
		if(rdexb='1') then 
			nextstate <= lee0;
		else				
			nextstate <= esplee1;
		end if;	
	when esplee1 =>--esperar a leer
		wrint<='0';rdint<='0';aleint<='0';nibble<='0';		
		if(wrexb='1')and(rdexb='0') then
			nextstate <= esplee1;
		elsif(wrexb='0')and(rdexb='0') then
			nextstate <= espdir;
		else
			nextstate <= lee1;
		end if;
	when lee1 =>--leer nibble mas significativo
		wrint<='0';aleint<='0';		
		rdint<='1';
		nibble<='1';--se ha de capturar el bit de nibble tambien
		if(wrexb='1')and(rdexb='1') then 
			nextstate <= reposo;
		else				
			nextstate <= lee1;
		end if;	
	end case;
end process;
synch: process(clk,rst)
begin
	if(rst='1') then
		prestate<=reposo;
	elsif (clk'event) and (clk='1') then
		prestate<=nextstate;
	end if;
end process;
end fsmrdwr_arch;
--Read Nibbles Mux
--Miguel A. Aguirre Echanove. University of Sevilla (SPAIN)
--Dpt. of Ingenieria Electronica. [e-mail]
--
library IEEE;
use IEEE.std_logic_1164.all;

entity spp_Muxsal is
    port (
        I0: in STD_LOGIC;
        I1: in STD_LOGIC;
        I2: in STD_LOGIC;
        I3: in STD_LOGIC;
        I4: in STD_LOGIC;
        I5: in STD_LOGIC;
        I6: in STD_LOGIC;
        I7: in STD_LOGIC;
        Nibble: in STD_LOGIC;
        datard: out STD_LOGIC_VECTOR (4 downto 0)
    );
end spp_Muxsal;

architecture Muxsal_arch of spp_Muxsal is
begin
process(I0,I1,I2,I3,I4,I5,I6,I7,Nibble)
begin
	if(Nibble='0') then
	    datard(0)<=I0;
	    datard(1)<=I1;
	    datard(2)<=I2;
	    datard(3)<=I3;
	else
	    datard(0)<=I4;
	    datard(1)<=I5;
	    datard(2)<=I6;
	    datard(3)<=I7;
	end if;
	datard(4)<=Nibble;
end process;	    
end Muxsal_arch;