📄 multiplexor.vhd
字号:
library IEEE;
use IEEE.std_logic_1164.all;
entity multiplexor is
port (
elige: in STD_LOGIC_VECTOR (1 downto 0);
dirpro: in STD_LOGIC_VECTOR (14 downto 0);
dirorig: in STD_LOGIC_VECTOR (14 downto 0);
dircom: in STD_LOGIC_VECTOR (14 downto 0);
direccion: out STD_LOGIC_VECTOR (14 downto 0)
);
end multiplexor;
architecture multiplexor_arch of multiplexor is
begin
process(elige, dirorig, dirpro, dircom)
begin
case elige is
when "00" => direccion<=dircom;
when "01" => direccion<=dirpro;
when "10" => direccion<=dirorig;
when others => direccion<=dirpro;
end case;
end process;
end multiplexor_arch;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -