monitor.vhd

VHDL 实现的图像增强

ENTITY monitor IS
  GENERIC( CONSTANT fileo: IN  STRING  := "u:videooutput.hex")  ; -- File name
  PORT(    SIGNAL   vdat:      IN STD_LOGIC_VECTOR (7 DOWNTO 0) ; -- Data
           SIGNAL   clk:       IN STD_LOGIC              := '0' ; -- Clock
           SIGNAL   n_hs:      IN STD_LOGIC              := '1' ; -- Horizontal Sync
           SIGNAL   n_vs:       IN STD_LOGIC              := '1' ; -- Vertical Sync
           SIGNAL   dv:         IN STD_LOGIC              := '0'); -- Data valid
END monitor;
-------------------------------------------------------------------------------
ARCHITECTURE behav OF monitor IS
  FILE     image:     hex_image_file IS OUT fileo                 ;
BEGIN
  ---- Data writing process ----------------------------------------------------------------
  pm1: PROCESS (clk)
   VARIABLE nib:         STD_LOGIC_VECTOR (3 DOWNTO 0);
   VARIABLE hex_nib:     hex;
   VARIABLE chr:         CHARACTER;
  BEGIN
     IF clk='1' THEN                        --signals are sampled at rising edge
      IF dv = '1' THEN                          -- If is data valid
        nib := vdat(7 DOWNTO 4); -- converted to hex (MS nibble)
        std2hex(nib,hex_nib);
        hex2chr(hex_nib,chr);
        WRITE(image,chr); -- and written into file
        std2hex(vdat(3 DOWNTO 0),hex_nib); -- converted to hex (LS nibble)
        hex2chr(hex_nib,chr);
        WRITE(image,chr); -- and written into file
      END IF;
    END IF;
  END PROCESS;
  ---- Horizontal sync pulse writing -------------------------------------------------------
  pm2: PROCESS (n_hs)
  BEGIN
    IF (n_hs'EVENT AND n_hs='0' AND n_vs='1') THEN
      WRITE(image,CR);   -- CR-LF are written into file
      WRITE(image,LF);
    END IF;
  END PROCESS;
  ---- Vertical sync pulse writing ---------------------------------------------------------
  pm3: PROCESS (n_vs)
  BEGIN
    IF (n_vs'EVENT AND n_vs='0') THEN
      WRITE(image,'*');  -- An asterisk is written into file
    END IF;
  END PROCESS;
END;