ssd.vhd

弦波產生+七段顯示器顯示目前該弦波點之數值

-- VHDL Model Created from ECS Symbol SSD.sym -- Mar 13 21:35:47 2006

library IEEE;
   use IEEE.std_logic_1164.all;
   use IEEE.std_logic_arith.all;
--library STD;
--   use STD.textio.all;

entity SSD is
      Port (       HEX_in : In   Unsigned (3 downto 0);
                   SSD_out : Out   std_logic_vector(6 downto 0));
end SSD;

architecture BEHAVIORAL of SSD is

   begin
   
process(HEX_in)
begin
      ---- BCD to SSD conversion: --------
      CASE conv_integer(HEX_in) IS    
		 WHEN 0  => SSD_out <= "1000000";                   
         WHEN 1  => SSD_out <= "1111001";	-- ---t----   
         WHEN 2  => SSD_out <= "0100100"; 	-- |	  |     
         WHEN 3  => SSD_out <= "0110000"; 	-- lt	 rt     
         WHEN 4  => SSD_out <= "0011001"; 	-- |	  |     
         WHEN 5  => SSD_out <= "0010010"; 	-- ---m----   
         WHEN 6  => SSD_out <= "0000010"; 	-- |	  |     
         WHEN 7  => SSD_out <= "1111000"; 	-- lb	 rb     
         WHEN 8  => SSD_out <= "0000000"; 	-- |	  |     
         WHEN 9  => SSD_out <= "0011000"; 	-- ---b----   
         WHEN 10 => SSD_out <= "0001000";                
         WHEN 11 => SSD_out <= "0000011";               
		 WHEN 12 => SSD_out <= "1000110";               
		 WHEN 13 => SSD_out <= "0100001";               
		 WHEN 14 => SSD_out <= "0000110";               
		 WHEN 15 => SSD_out <= "0001110";                 		 
         WHEN OTHERS => NULL;                
      END CASE;                           		
end process;

end BEHAVIORAL;

configuration CFG_SSD of SSD is
   for BEHAVIORAL

   end for;

end CFG_SSD;