ffd.v

Verilog 编写的fir滤波器

module FFD(reset,clk2,n,P3,P2);  
input reset,clk2;
input [15:0] P3;
input [3:0] n;
output[15:0] P2;
reg[15:0] P2;
always@(negedge clk2 or negedge reset)
 begin
    if(!reset)  P2=0; 
    else 
      begin
         case(n)
           0:   P2=0;
           1:   P2=0;
           2:   P2=P3; 
           3:   P2=P3; 
           4:   P2=P3;
           5:   P2=P3; 
           6:   P2=P3; 
           7:   P2=P3;
           8:   P2=P3;
           default: P2=P3; 
        endcase
      end
end
endmodule