top.v

Verilog 编写的fir滤波器

module top(clk1,clk2,reset,xin,hin,yout);
input clk1,clk2,reset;
input[7:0] xin;
input[63:0] hin;
output[15:0] yout;
wire [127:0] x1;
wire [7:0] x2,x3;
wire [8:0] x4;
wire [15:0] P1,P2,P3,yout;
wire [7:0] h;
wire OE;
wire[3:0] n;
controller mycontroller(clk1,clk2,n,OE);
shifter shifter1(clk1,reset,xin,x1);
mux mux1(reset,clk2,n,x1,x2,x3);
adder adder1(x2,x3,x4);
muxh muxh1(reset,clk2,n,hin,h);
multiple multiple1(h,clk2,x4,reset,P1);
adders adders1(P1,P2,P3);
FFD FFD1(reset,clk2,n,P3,P2);  
FFD2 FFD2(OE,reset,P2,yout);  
endmodule